cdc4864919fdea367b1b187aef48b8a89ce437d6
[glsdk/glsdk-u-boot.git] / arch / arm / cpu / armv7 / omap5 / prcm-regs.c
1 /*
2  *
3  * HW regs data for OMAP5 Soc
4  *
5  * (C) Copyright 2013
6  * Texas Instruments, <www.ti.com>
7  *
8  * Sricharan R <r.sricharan@ti.com>
9  *
10  * See file CREDITS for list of people who contributed to this
11  * project.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License as
15  * published by the Free Software Foundation; either version 2 of
16  * the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26  * MA 02111-1307 USA
27  */
29 #include <asm/omap_common.h>
31 struct prcm_regs const omap5_es1_prcm = {
32         /* cm1.ckgen */
33         .cm_clksel_core = 0x4a004100,
34         .cm_clksel_abe = 0x4a004108,
35         .cm_dll_ctrl = 0x4a004110,
36         .cm_clkmode_dpll_core = 0x4a004120,
37         .cm_idlest_dpll_core = 0x4a004124,
38         .cm_autoidle_dpll_core = 0x4a004128,
39         .cm_clksel_dpll_core = 0x4a00412c,
40         .cm_div_m2_dpll_core = 0x4a004130,
41         .cm_div_m3_dpll_core = 0x4a004134,
42         .cm_div_h11_dpll_core = 0x4a004138,
43         .cm_div_h12_dpll_core = 0x4a00413c,
44         .cm_div_h13_dpll_core = 0x4a004140,
45         .cm_div_h14_dpll_core = 0x4a004144,
46         .cm_ssc_deltamstep_dpll_core = 0x4a004148,
47         .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
48         .cm_emu_override_dpll_core = 0x4a004150,
49         .cm_div_h22_dpllcore = 0x4a004154,
50         .cm_div_h23_dpll_core = 0x4a004158,
51         .cm_clkmode_dpll_mpu = 0x4a004160,
52         .cm_idlest_dpll_mpu = 0x4a004164,
53         .cm_autoidle_dpll_mpu = 0x4a004168,
54         .cm_clksel_dpll_mpu = 0x4a00416c,
55         .cm_div_m2_dpll_mpu = 0x4a004170,
56         .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
57         .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
58         .cm_bypclk_dpll_mpu = 0x4a00419c,
59         .cm_clkmode_dpll_iva = 0x4a0041a0,
60         .cm_idlest_dpll_iva = 0x4a0041a4,
61         .cm_autoidle_dpll_iva = 0x4a0041a8,
62         .cm_clksel_dpll_iva = 0x4a0041ac,
63         .cm_div_h11_dpll_iva = 0x4a0041b8,
64         .cm_div_h12_dpll_iva = 0x4a0041bc,
65         .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
66         .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
67         .cm_bypclk_dpll_iva = 0x4a0041dc,
68         .cm_clkmode_dpll_abe = 0x4a0041e0,
69         .cm_idlest_dpll_abe = 0x4a0041e4,
70         .cm_autoidle_dpll_abe = 0x4a0041e8,
71         .cm_clksel_dpll_abe = 0x4a0041ec,
72         .cm_div_m2_dpll_abe = 0x4a0041f0,
73         .cm_div_m3_dpll_abe = 0x4a0041f4,
74         .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
75         .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
76         .cm_clkmode_dpll_ddrphy = 0x4a004220,
77         .cm_idlest_dpll_ddrphy = 0x4a004224,
78         .cm_autoidle_dpll_ddrphy = 0x4a004228,
79         .cm_clksel_dpll_ddrphy = 0x4a00422c,
80         .cm_div_m2_dpll_ddrphy = 0x4a004230,
81         .cm_div_h11_dpll_ddrphy = 0x4a004238,
82         .cm_div_h12_dpll_ddrphy = 0x4a00423c,
83         .cm_div_h13_dpll_ddrphy = 0x4a004240,
84         .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
85         .cm_shadow_freq_config1 = 0x4a004260,
86         .cm_mpu_mpu_clkctrl = 0x4a004320,
88         /* cm1.dsp */
89         .cm_dsp_clkstctrl = 0x4a004400,
90         .cm_dsp_dsp_clkctrl = 0x4a004420,
92         /* cm1.abe */
93         .cm1_abe_clkstctrl = 0x4a004500,
94         .cm1_abe_l4abe_clkctrl = 0x4a004520,
95         .cm1_abe_aess_clkctrl = 0x4a004528,
96         .cm1_abe_pdm_clkctrl = 0x4a004530,
97         .cm1_abe_dmic_clkctrl = 0x4a004538,
98         .cm1_abe_mcasp_clkctrl = 0x4a004540,
99         .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
100         .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
101         .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
102         .cm1_abe_slimbus_clkctrl = 0x4a004560,
103         .cm1_abe_timer5_clkctrl = 0x4a004568,
104         .cm1_abe_timer6_clkctrl = 0x4a004570,
105         .cm1_abe_timer7_clkctrl = 0x4a004578,
106         .cm1_abe_timer8_clkctrl = 0x4a004580,
107         .cm1_abe_wdt3_clkctrl = 0x4a004588,
109         /* cm2.ckgen */
110         .cm_clksel_mpu_m3_iss_root = 0x4a008100,
111         .cm_clksel_usb_60mhz = 0x4a008104,
112         .cm_scale_fclk = 0x4a008108,
113         .cm_core_dvfs_perf1 = 0x4a008110,
114         .cm_core_dvfs_perf2 = 0x4a008114,
115         .cm_core_dvfs_perf3 = 0x4a008118,
116         .cm_core_dvfs_perf4 = 0x4a00811c,
117         .cm_core_dvfs_current = 0x4a008124,
118         .cm_iva_dvfs_perf_tesla = 0x4a008128,
119         .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
120         .cm_iva_dvfs_perf_abe = 0x4a008130,
121         .cm_iva_dvfs_current = 0x4a008138,
122         .cm_clkmode_dpll_per = 0x4a008140,
123         .cm_idlest_dpll_per = 0x4a008144,
124         .cm_autoidle_dpll_per = 0x4a008148,
125         .cm_clksel_dpll_per = 0x4a00814c,
126         .cm_div_m2_dpll_per = 0x4a008150,
127         .cm_div_m3_dpll_per = 0x4a008154,
128         .cm_div_h11_dpll_per = 0x4a008158,
129         .cm_div_h12_dpll_per = 0x4a00815c,
130         .cm_div_h14_dpll_per = 0x4a008164,
131         .cm_ssc_deltamstep_dpll_per = 0x4a008168,
132         .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
133         .cm_emu_override_dpll_per = 0x4a008170,
134         .cm_clkmode_dpll_usb = 0x4a008180,
135         .cm_idlest_dpll_usb = 0x4a008184,
136         .cm_autoidle_dpll_usb = 0x4a008188,
137         .cm_clksel_dpll_usb = 0x4a00818c,
138         .cm_div_m2_dpll_usb = 0x4a008190,
139         .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
140         .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
141         .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
142         .cm_clkmode_dpll_unipro = 0x4a0081c0,
143         .cm_idlest_dpll_unipro = 0x4a0081c4,
144         .cm_autoidle_dpll_unipro = 0x4a0081c8,
145         .cm_clksel_dpll_unipro = 0x4a0081cc,
146         .cm_div_m2_dpll_unipro = 0x4a0081d0,
147         .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
148         .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
150         /* cm2.core */
151         .cm_coreaon_bandgap_clkctrl = 0x4a008648,
152         .cm_l3_1_clkstctrl = 0x4a008700,
153         .cm_l3_1_dynamicdep = 0x4a008708,
154         .cm_l3_1_l3_1_clkctrl = 0x4a008720,
155         .cm_l3_2_clkstctrl = 0x4a008800,
156         .cm_l3_2_dynamicdep = 0x4a008808,
157         .cm_l3_2_l3_2_clkctrl = 0x4a008820,
158         .cm_l3_2_gpmc_clkctrl = 0x4a008828,
159         .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
160         .cm_mpu_m3_clkstctrl = 0x4a008900,
161         .cm_mpu_m3_staticdep = 0x4a008904,
162         .cm_mpu_m3_dynamicdep = 0x4a008908,
163         .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
164         .cm_sdma_clkstctrl = 0x4a008a00,
165         .cm_sdma_staticdep = 0x4a008a04,
166         .cm_sdma_dynamicdep = 0x4a008a08,
167         .cm_sdma_sdma_clkctrl = 0x4a008a20,
168         .cm_memif_clkstctrl = 0x4a008b00,
169         .cm_memif_dmm_clkctrl = 0x4a008b20,
170         .cm_memif_emif_fw_clkctrl = 0x4a008b28,
171         .cm_memif_emif_1_clkctrl = 0x4a008b30,
172         .cm_memif_emif_2_clkctrl = 0x4a008b38,
173         .cm_memif_dll_clkctrl = 0x4a008b40,
174         .cm_memif_emif_h1_clkctrl = 0x4a008b50,
175         .cm_memif_emif_h2_clkctrl = 0x4a008b58,
176         .cm_memif_dll_h_clkctrl = 0x4a008b60,
177         .cm_c2c_clkstctrl = 0x4a008c00,
178         .cm_c2c_staticdep = 0x4a008c04,
179         .cm_c2c_dynamicdep = 0x4a008c08,
180         .cm_c2c_sad2d_clkctrl = 0x4a008c20,
181         .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
182         .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
183         .cm_l4cfg_clkstctrl = 0x4a008d00,
184         .cm_l4cfg_dynamicdep = 0x4a008d08,
185         .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
186         .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
187         .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
188         .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
189         .cm_l3instr_clkstctrl = 0x4a008e00,
190         .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
191         .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
192         .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
194         /* cm2.ivahd */
195         .cm_ivahd_clkstctrl = 0x4a008f00,
196         .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
197         .cm_ivahd_sl2_clkctrl = 0x4a008f28,
199         /* cm2.cam */
200         .cm_cam_clkstctrl = 0x4a009000,
201         .cm_cam_iss_clkctrl = 0x4a009020,
202         .cm_cam_fdif_clkctrl = 0x4a009028,
204         /* cm2.dss */
205         .cm_dss_clkstctrl = 0x4a009100,
206         .cm_dss_dss_clkctrl = 0x4a009120,
208         /* cm2.sgx */
209         .cm_sgx_clkstctrl = 0x4a009200,
210         .cm_sgx_sgx_clkctrl = 0x4a009220,
212         /* cm2.l3init */
213         .cm_l3init_clkstctrl = 0x4a009300,
214         .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
215         .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
216         .cm_l3init_hsi_clkctrl = 0x4a009338,
217         .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
218         .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
219         .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
220         .cm_l3init_p1500_clkctrl = 0x4a009378,
221         .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
222         .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
224         /* cm2.l4per */
225         .cm_l4per_clkstctrl = 0x4a009400,
226         .cm_l4per_dynamicdep = 0x4a009408,
227         .cm_l4per_adc_clkctrl = 0x4a009420,
228         .cm_l4per_gptimer10_clkctrl = 0x4a009428,
229         .cm_l4per_gptimer11_clkctrl = 0x4a009430,
230         .cm_l4per_gptimer2_clkctrl = 0x4a009438,
231         .cm_l4per_gptimer3_clkctrl = 0x4a009440,
232         .cm_l4per_gptimer4_clkctrl = 0x4a009448,
233         .cm_l4per_gptimer9_clkctrl = 0x4a009450,
234         .cm_l4per_elm_clkctrl = 0x4a009458,
235         .cm_l4per_gpio2_clkctrl = 0x4a009460,
236         .cm_l4per_gpio3_clkctrl = 0x4a009468,
237         .cm_l4per_gpio4_clkctrl = 0x4a009470,
238         .cm_l4per_gpio5_clkctrl = 0x4a009478,
239         .cm_l4per_gpio6_clkctrl = 0x4a009480,
240         .cm_l4per_hdq1w_clkctrl = 0x4a009488,
241         .cm_l4per_hecc1_clkctrl = 0x4a009490,
242         .cm_l4per_hecc2_clkctrl = 0x4a009498,
243         .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
244         .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
245         .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
246         .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
247         .cm_l4per_l4per_clkctrl = 0x4a0094c0,
248         .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
249         .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
250         .cm_l4per_mgate_clkctrl = 0x4a0094e8,
251         .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
252         .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
253         .cm_l4per_mcspi3_clkctrl = 0x4a009500,
254         .cm_l4per_mcspi4_clkctrl = 0x4a009508,
255         .cm_l4per_gpio7_clkctrl = 0x4a009510,
256         .cm_l4per_gpio8_clkctrl = 0x4a009518,
257         .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
258         .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
259         .cm_l4per_msprohg_clkctrl = 0x4a009530,
260         .cm_l4per_slimbus2_clkctrl = 0x4a009538,
261         .cm_l4per_uart1_clkctrl = 0x4a009540,
262         .cm_l4per_uart2_clkctrl = 0x4a009548,
263         .cm_l4per_uart3_clkctrl = 0x4a009550,
264         .cm_l4per_uart4_clkctrl = 0x4a009558,
265         .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
266         .cm_l4per_i2c5_clkctrl = 0x4a009568,
267         .cm_l4per_uart5_clkctrl = 0x4a009570,
268         .cm_l4per_uart6_clkctrl = 0x4a009578,
269         .cm_l4sec_clkstctrl = 0x4a009580,
270         .cm_l4sec_staticdep = 0x4a009584,
271         .cm_l4sec_dynamicdep = 0x4a009588,
272         .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
273         .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
274         .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
275         .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
276         .cm_l4sec_rng_clkctrl = 0x4a0095c0,
277         .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
278         .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
280         /* l4 wkup regs */
281         .cm_abe_pll_ref_clksel = 0x4ae0610c,
282         .cm_sys_clksel = 0x4ae06110,
283         .cm_wkup_clkstctrl = 0x4ae07800,
284         .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
285         .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
286         .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
287         .cm_wkup_gpio1_clkctrl = 0x4ae07838,
288         .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
289         .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
290         .cm_wkup_synctimer_clkctrl = 0x4ae07850,
291         .cm_wkup_usim_clkctrl = 0x4ae07858,
292         .cm_wkup_sarram_clkctrl = 0x4ae07860,
293         .cm_wkup_keyboard_clkctrl = 0x4ae07878,
294         .cm_wkup_rtc_clkctrl = 0x4ae07880,
295         .cm_wkup_bandgap_clkctrl = 0x4ae07888,
296         .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
297         .prm_vc_val_bypass = 0x4ae07ba0,
298         .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
299         .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
300         .prm_sldo_core_setup = 0x4ae07bc4,
301         .prm_sldo_core_ctrl = 0x4ae07bc8,
302         .prm_sldo_mpu_setup = 0x4ae07bcc,
303         .prm_sldo_mpu_ctrl = 0x4ae07bd0,
304         .prm_sldo_mm_setup = 0x4ae07bd4,
305         .prm_sldo_mm_ctrl = 0x4ae07bd8,
306 };