1 /*
2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
3 *
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
5 *
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
32 #include <asm-offsets.h>
33 #include <config.h>
34 #include <version.h>
35 #include <asm/system.h>
36 #include <linux/linkage.h>
38 .globl _start
39 _start: b reset
40 ldr pc, _undefined_instruction
41 ldr pc, _software_interrupt
42 ldr pc, _prefetch_abort
43 ldr pc, _data_abort
44 ldr pc, _not_used
45 ldr pc, _irq
46 ldr pc, _fiq
47 #ifdef CONFIG_SPL_BUILD
48 _undefined_instruction: .word _undefined_instruction
49 _software_interrupt: .word _software_interrupt
50 _prefetch_abort: .word _prefetch_abort
51 _data_abort: .word _data_abort
52 _not_used: .word _not_used
53 _irq: .word _irq
54 _fiq: .word _fiq
55 _pad: .word 0x12345678 /* now 16*4=64 */
56 #else
57 _undefined_instruction: .word undefined_instruction
58 _software_interrupt: .word software_interrupt
59 _prefetch_abort: .word prefetch_abort
60 _data_abort: .word data_abort
61 _not_used: .word not_used
62 _irq: .word irq
63 _fiq: .word fiq
64 _pad: .word 0x12345678 /* now 16*4=64 */
65 #endif /* CONFIG_SPL_BUILD */
67 .global _end_vect
68 _end_vect:
70 .balignl 16,0xdeadbeef
71 /*************************************************************************
72 *
73 * Startup Code (reset vector)
74 *
75 * do important init only if we don't start from memory!
76 * setup Memory and board specific bits prior to relocation.
77 * relocate armboot to ram
78 * setup stack
79 *
80 *************************************************************************/
82 .globl _TEXT_BASE
83 _TEXT_BASE:
84 .word CONFIG_SYS_TEXT_BASE
86 /*
87 * These are defined in the board-specific linker script.
88 */
89 .globl _bss_start_ofs
90 _bss_start_ofs:
91 .word __bss_start - _start
93 .global _image_copy_end_ofs
94 _image_copy_end_ofs:
95 .word __image_copy_end - _start
97 .globl _bss_end_ofs
98 _bss_end_ofs:
99 .word __bss_end - _start
101 .globl _end_ofs
102 _end_ofs:
103 .word _end - _start
105 #ifdef CONFIG_USE_IRQ
106 /* IRQ stack memory (calculated at run-time) */
107 .globl IRQ_STACK_START
108 IRQ_STACK_START:
109 .word 0x0badc0de
111 /* IRQ stack memory (calculated at run-time) */
112 .globl FIQ_STACK_START
113 FIQ_STACK_START:
114 .word 0x0badc0de
115 #endif
117 /* IRQ stack memory (calculated at run-time) + 8 bytes */
118 .globl IRQ_STACK_START_IN
119 IRQ_STACK_START_IN:
120 .word 0x0badc0de
122 /*
123 * the actual reset code
124 */
126 reset:
127 bl save_boot_params
128 /*
129 * set the cpu to SVC32 mode
130 */
131 mrs r0, cpsr
132 bic r0, r0, #0x1f
133 orr r0, r0, #0xd3
134 msr cpsr,r0
136 /*
137 * Setup vector:
138 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
139 * Continue to use ROM code vector only in OMAP4 spl)
140 */
141 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
142 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
143 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
144 bic r0, #CR_V @ V = 0
145 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
147 /* Set vector address in CP15 VBAR register */
148 ldr r0, =_start
149 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
150 #endif
152 /* the mask ROM code should have PLL and others stable */
153 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
154 bl cpu_init_cp15
155 bl cpu_init_crit
156 #endif
158 bl _main
160 /*------------------------------------------------------------------------------*/
162 #ifndef CONFIG_SPL_BUILD
163 /*
164 * void relocate_code (addr_sp, gd, addr_moni)
165 *
166 * This "function" does not return, instead it continues in RAM
167 * after relocating the monitor code.
168 *
169 */
170 ENTRY(relocate_code)
171 mov r4, r0 /* save addr_sp */
172 mov r5, r1 /* save addr of gd */
173 mov r6, r2 /* save addr of destination */
175 adr r0, _start
176 cmp r0, r6
177 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
178 beq relocate_done /* skip relocation */
179 mov r1, r6 /* r1 <- scratch for copy_loop */
180 ldr r3, _image_copy_end_ofs
181 add r2, r0, r3 /* r2 <- source end address */
183 copy_loop:
184 ldmia r0!, {r9-r10} /* copy from source address [r0] */
185 stmia r1!, {r9-r10} /* copy to target address [r1] */
186 cmp r0, r2 /* until source end address [r2] */
187 blo copy_loop
189 /*
190 * fix .rel.dyn relocations
191 */
192 ldr r0, _TEXT_BASE /* r0 <- Text base */
193 sub r9, r6, r0 /* r9 <- relocation offset */
194 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
195 add r10, r10, r0 /* r10 <- sym table in FLASH */
196 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
197 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
198 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
199 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
200 fixloop:
201 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
202 add r0, r0, r9 /* r0 <- location to fix up in RAM */
203 ldr r1, [r2, #4]
204 and r7, r1, #0xff
205 cmp r7, #23 /* relative fixup? */
206 beq fixrel
207 cmp r7, #2 /* absolute fixup? */
208 beq fixabs
209 /* ignore unknown type of fixup */
210 b fixnext
211 fixabs:
212 /* absolute fix: set location to (offset) symbol value */
213 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
214 add r1, r10, r1 /* r1 <- address of symbol in table */
215 ldr r1, [r1, #4] /* r1 <- symbol value */
216 add r1, r1, r9 /* r1 <- relocated sym addr */
217 b fixnext
218 fixrel:
219 /* relative fix: increase location by offset */
220 ldr r1, [r0]
221 add r1, r1, r9
222 fixnext:
223 str r1, [r0]
224 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
225 cmp r2, r3
226 blo fixloop
228 relocate_done:
230 bx lr
232 _rel_dyn_start_ofs:
233 .word __rel_dyn_start - _start
234 _rel_dyn_end_ofs:
235 .word __rel_dyn_end - _start
236 _dynsym_start_ofs:
237 .word __dynsym_start - _start
238 ENDPROC(relocate_code)
240 #endif
242 ENTRY(c_runtime_cpu_setup)
243 /*
244 * If I-cache is enabled invalidate it
245 */
246 #ifndef CONFIG_SYS_ICACHE_OFF
247 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
248 mcr p15, 0, r0, c7, c10, 4 @ DSB
249 mcr p15, 0, r0, c7, c5, 4 @ ISB
250 #endif
251 /*
252 * Move vector table
253 */
254 #if !defined(CONFIG_TEGRA)
255 /* Set vector address in CP15 VBAR register */
256 ldr r0, =_start
257 add r0, r0, r9
258 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
259 #endif /* !Tegra */
261 bx lr
263 ENDPROC(c_runtime_cpu_setup)
265 /*************************************************************************
266 *
267 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
268 * __attribute__((weak));
269 *
270 * Stack pointer is not yet initialized at this moment
271 * Don't save anything to stack even if compiled with -O0
272 *
273 *************************************************************************/
274 ENTRY(save_boot_params)
275 bx lr @ back to my caller
276 ENDPROC(save_boot_params)
277 .weak save_boot_params
279 /*************************************************************************
280 *
281 * cpu_init_cp15
282 *
283 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
284 * CONFIG_SYS_ICACHE_OFF is defined.
285 *
286 *************************************************************************/
287 ENTRY(cpu_init_cp15)
288 /*
289 * Invalidate L1 I/D
290 */
291 mov r0, #0 @ set up for MCR
292 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
293 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
294 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
295 mcr p15, 0, r0, c7, c10, 4 @ DSB
296 mcr p15, 0, r0, c7, c5, 4 @ ISB
298 /*
299 * disable MMU stuff and caches
300 */
301 mrc p15, 0, r0, c1, c0, 0
302 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
303 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
304 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
305 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
306 #ifdef CONFIG_SYS_ICACHE_OFF
307 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
308 #else
309 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
310 #endif
311 mcr p15, 0, r0, c1, c0, 0
313 #ifdef CONFIG_ARM_ERRATA_742230
314 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
315 orr r0, r0, #1 << 4 @ set bit #4
316 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
317 #endif
319 #ifdef CONFIG_ARM_ERRATA_743622
320 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
321 orr r0, r0, #1 << 6 @ set bit #6
322 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
323 #endif
325 #ifdef CONFIG_ARM_ERRATA_751472
326 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
327 orr r0, r0, #1 << 11 @ set bit #11
328 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
329 #endif
331 mov pc, lr @ back to my caller
332 ENDPROC(cpu_init_cp15)
334 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
335 /*************************************************************************
336 *
337 * CPU_init_critical registers
338 *
339 * setup important registers
340 * setup memory timing
341 *
342 *************************************************************************/
343 ENTRY(cpu_init_crit)
344 /*
345 * Jump to board specific initialization...
346 * The Mask ROM will have already initialized
347 * basic memory. Go here to bump up clock rate and handle
348 * wake up conditions.
349 */
350 b lowlevel_init @ go setup pll,mux,memory
351 ENDPROC(cpu_init_crit)
352 #endif
354 #ifndef CONFIG_SPL_BUILD
355 /*
356 *************************************************************************
357 *
358 * Interrupt handling
359 *
360 *************************************************************************
361 */
362 @
363 @ IRQ stack frame.
364 @
365 #define S_FRAME_SIZE 72
367 #define S_OLD_R0 68
368 #define S_PSR 64
369 #define S_PC 60
370 #define S_LR 56
371 #define S_SP 52
373 #define S_IP 48
374 #define S_FP 44
375 #define S_R10 40
376 #define S_R9 36
377 #define S_R8 32
378 #define S_R7 28
379 #define S_R6 24
380 #define S_R5 20
381 #define S_R4 16
382 #define S_R3 12
383 #define S_R2 8
384 #define S_R1 4
385 #define S_R0 0
387 #define MODE_SVC 0x13
388 #define I_BIT 0x80
390 /*
391 * use bad_save_user_regs for abort/prefetch/undef/swi ...
392 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
393 */
395 .macro bad_save_user_regs
396 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
397 @ user stack
398 stmia sp, {r0 - r12} @ Save user registers (now in
399 @ svc mode) r0-r12
400 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
401 @ stack
402 ldmia r2, {r2 - r3} @ get values for "aborted" pc
403 @ and cpsr (into parm regs)
404 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
406 add r5, sp, #S_SP
407 mov r1, lr
408 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
409 mov r0, sp @ save current stack into r0
410 @ (param register)
411 .endm
413 .macro irq_save_user_regs
414 sub sp, sp, #S_FRAME_SIZE
415 stmia sp, {r0 - r12} @ Calling r0-r12
416 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
417 @ a reserved stack spot would
418 @ be good.
419 stmdb r8, {sp, lr}^ @ Calling SP, LR
420 str lr, [r8, #0] @ Save calling PC
421 mrs r6, spsr
422 str r6, [r8, #4] @ Save CPSR
423 str r0, [r8, #8] @ Save OLD_R0
424 mov r0, sp
425 .endm
427 .macro irq_restore_user_regs
428 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
429 mov r0, r0
430 ldr lr, [sp, #S_PC] @ Get PC
431 add sp, sp, #S_FRAME_SIZE
432 subs pc, lr, #4 @ return & move spsr_svc into
433 @ cpsr
434 .endm
436 .macro get_bad_stack
437 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
438 @ in banked mode)
440 str lr, [r13] @ save caller lr in position 0
441 @ of saved stack
442 mrs lr, spsr @ get the spsr
443 str lr, [r13, #4] @ save spsr in position 1 of
444 @ saved stack
446 mov r13, #MODE_SVC @ prepare SVC-Mode
447 @ msr spsr_c, r13
448 msr spsr, r13 @ switch modes, make sure
449 @ moves will execute
450 mov lr, pc @ capture return pc
451 movs pc, lr @ jump to next instruction &
452 @ switch modes.
453 .endm
455 .macro get_bad_stack_swi
456 sub r13, r13, #4 @ space on current stack for
457 @ scratch reg.
458 str r0, [r13] @ save R0's value.
459 ldr r0, IRQ_STACK_START_IN @ get data regions start
460 @ spots for abort stack
461 str lr, [r0] @ save caller lr in position 0
462 @ of saved stack
463 mrs r0, spsr @ get the spsr
464 str lr, [r0, #4] @ save spsr in position 1 of
465 @ saved stack
466 ldr r0, [r13] @ restore r0
467 add r13, r13, #4 @ pop stack entry
468 .endm
470 .macro get_irq_stack @ setup IRQ stack
471 ldr sp, IRQ_STACK_START
472 .endm
474 .macro get_fiq_stack @ setup FIQ stack
475 ldr sp, FIQ_STACK_START
476 .endm
478 /*
479 * exception handlers
480 */
481 .align 5
482 undefined_instruction:
483 get_bad_stack
484 bad_save_user_regs
485 bl do_undefined_instruction
487 .align 5
488 software_interrupt:
489 get_bad_stack_swi
490 bad_save_user_regs
491 bl do_software_interrupt
493 .align 5
494 prefetch_abort:
495 get_bad_stack
496 bad_save_user_regs
497 bl do_prefetch_abort
499 .align 5
500 data_abort:
501 get_bad_stack
502 bad_save_user_regs
503 bl do_data_abort
505 .align 5
506 not_used:
507 get_bad_stack
508 bad_save_user_regs
509 bl do_not_used
511 #ifdef CONFIG_USE_IRQ
513 .align 5
514 irq:
515 get_irq_stack
516 irq_save_user_regs
517 bl do_irq
518 irq_restore_user_regs
520 .align 5
521 fiq:
522 get_fiq_stack
523 /* someone ought to write a more effective fiq_save_user_regs */
524 irq_save_user_regs
525 bl do_fiq
526 irq_restore_user_regs
528 #else
530 .align 5
531 irq:
532 get_bad_stack
533 bad_save_user_regs
534 bl do_irq
536 .align 5
537 fiq:
538 get_bad_stack
539 bad_save_user_regs
540 bl do_fiq
542 #endif /* CONFIG_USE_IRQ */
543 #endif /* CONFIG_SPL_BUILD */