1 /*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 #include <common.h>
25 #include <asm/io.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/funcmux.h>
28 #include <asm/arch/tegra.h>
29 #include <asm/arch-tegra/board.h>
30 #include <asm/arch-tegra/pmc.h>
31 #include <asm/arch-tegra/sys_proto.h>
32 #include <asm/arch-tegra/warmboot.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 enum {
37 /* UARTs which we can enable */
38 UARTA = 1 << 0,
39 UARTB = 1 << 1,
40 UARTC = 1 << 2,
41 UARTD = 1 << 3,
42 UARTE = 1 << 4,
43 UART_COUNT = 5,
44 };
46 /*
47 * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
48 * so we are using this value to identify memory size.
49 */
51 unsigned int query_sdram_size(void)
52 {
53 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
54 u32 reg;
56 reg = readl(&pmc->pmc_scratch20);
57 debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
59 #if defined(CONFIG_TEGRA20)
60 /* bits 30:28 in OdmData are used for RAM size on T20 */
61 reg &= 0x70000000;
63 switch ((reg) >> 28) {
64 case 1:
65 return 0x10000000; /* 256 MB */
66 case 0:
67 case 2:
68 default:
69 return 0x20000000; /* 512 MB */
70 case 3:
71 return 0x40000000; /* 1GB */
72 }
73 #else /* Tegra30/Tegra114 */
74 /* bits 31:28 in OdmData are used for RAM size on T30 */
75 switch ((reg) >> 28) {
76 case 0:
77 case 1:
78 default:
79 return 0x10000000; /* 256 MB */
80 case 2:
81 return 0x20000000; /* 512 MB */
82 case 3:
83 return 0x30000000; /* 768 MB */
84 case 4:
85 return 0x40000000; /* 1GB */
86 case 8:
87 return 0x7ff00000; /* 2GB - 1MB */
88 }
89 #endif
90 }
92 int dram_init(void)
93 {
94 /* We do not initialise DRAM here. We just query the size */
95 gd->ram_size = query_sdram_size();
96 return 0;
97 }
99 #ifdef CONFIG_DISPLAY_BOARDINFO
100 int checkboard(void)
101 {
102 printf("Board: %s\n", sysinfo.board_string);
103 return 0;
104 }
105 #endif /* CONFIG_DISPLAY_BOARDINFO */
107 static int uart_configs[] = {
108 #if defined(CONFIG_TEGRA20)
109 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
110 FUNCMUX_UART1_UAA_UAB,
111 #elif defined(CONFIG_TEGRA_UARTA_GPU)
112 FUNCMUX_UART1_GPU,
113 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
114 FUNCMUX_UART1_SDIO1,
115 #else
116 FUNCMUX_UART1_IRRX_IRTX,
117 #endif
118 FUNCMUX_UART2_UAD,
119 -1,
120 FUNCMUX_UART4_GMC,
121 -1,
122 #elif defined(CONFIG_TEGRA30)
123 FUNCMUX_UART1_ULPI, /* UARTA */
124 -1,
125 -1,
126 -1,
127 -1,
128 #else /* Tegra114 */
129 -1,
130 -1,
131 -1,
132 FUNCMUX_UART4_GMI, /* UARTD */
133 -1,
134 #endif
135 };
137 /**
138 * Set up the specified uarts
139 *
140 * @param uarts_ids Mask containing UARTs to init (UARTx)
141 */
142 static void setup_uarts(int uart_ids)
143 {
144 static enum periph_id id_for_uart[] = {
145 PERIPH_ID_UART1,
146 PERIPH_ID_UART2,
147 PERIPH_ID_UART3,
148 PERIPH_ID_UART4,
149 PERIPH_ID_UART5,
150 };
151 size_t i;
153 for (i = 0; i < UART_COUNT; i++) {
154 if (uart_ids & (1 << i)) {
155 enum periph_id id = id_for_uart[i];
157 funcmux_select(id, uart_configs[i]);
158 clock_ll_start_uart(id);
159 }
160 }
161 }
163 void board_init_uart_f(void)
164 {
165 int uart_ids = 0; /* bit mask of which UART ids to enable */
167 #ifdef CONFIG_TEGRA_ENABLE_UARTA
168 uart_ids |= UARTA;
169 #endif
170 #ifdef CONFIG_TEGRA_ENABLE_UARTB
171 uart_ids |= UARTB;
172 #endif
173 #ifdef CONFIG_TEGRA_ENABLE_UARTC
174 uart_ids |= UARTC;
175 #endif
176 #ifdef CONFIG_TEGRA_ENABLE_UARTD
177 uart_ids |= UARTD;
178 #endif
179 #ifdef CONFIG_TEGRA_ENABLE_UARTE
180 uart_ids |= UARTE;
181 #endif
182 setup_uarts(uart_ids);
183 }
185 #ifndef CONFIG_SYS_DCACHE_OFF
186 void enable_caches(void)
187 {
188 /* Enable D-cache. I-cache is already enabled in start.S */
189 dcache_enable();
190 }
191 #endif