OMAP5: Adding correct Control id code for OMAP5430
[glsdk/glsdk-u-boot.git] / arch / arm / include / asm / arch-omap5 / omap.h
1 /*
2  * (C) Copyright 2010
3  * Texas Instruments, <www.ti.com>
4  *
5  * Authors:
6  *      Aneesh V <aneesh@ti.com>
7  *      Sricharan R <r.sricharan@ti.com>
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
28 #ifndef _OMAP5_H_
29 #define _OMAP5_H_
31 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
32 #include <asm/types.h>
33 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
35 /*
36  * L4 Peripherals - L4 Wakeup and L4 Core now
37  */
38 #define OMAP54XX_L4_CORE_BASE   0x4A000000
39 #define OMAP54XX_L4_WKUP_BASE   0x4Ae00000
40 #define OMAP54XX_L4_PER_BASE    0x48000000
42 #define OMAP54XX_DRAM_ADDR_SPACE_START  0x80000000
43 #define OMAP54XX_DRAM_ADDR_SPACE_END    0xFFFFFFFF
44 #define DRAM_ADDR_SPACE_START   OMAP54XX_DRAM_ADDR_SPACE_START
45 #define DRAM_ADDR_SPACE_END     OMAP54XX_DRAM_ADDR_SPACE_END
47 /* CONTROL */
48 #define CTRL_BASE               (OMAP54XX_L4_CORE_BASE + 0x2000)
49 #define CONTROL_PADCONF_CORE    (CTRL_BASE + 0x0800)
50 #define CONTROL_PADCONF_WKUP    (OMAP54XX_L4_WKUP_BASE + 0xc800)
52 /* LPDDR2 IO regs. To be verified */
53 #define LPDDR2_IO_REGS_BASE     0x4A100638
55 /* CONTROL_ID_CODE */
56 #define CONTROL_ID_CODE         (CTRL_BASE + 0x204)
58 /* To be verified */
59 #define OMAP5_CONTROL_ID_CODE_ES1_0     0x0B94202F
61 /* STD_FUSE_PROD_ID_1 */
62 #define STD_FUSE_PROD_ID_1              (CTRL_BASE + 0x218)
63 #define PROD_ID_1_SILICON_TYPE_SHIFT    16
64 #define PROD_ID_1_SILICON_TYPE_MASK     (3 << 16)
66 /* UART */
67 #define UART1_BASE              (OMAP54XX_L4_PER_BASE + 0x6a000)
68 #define UART2_BASE              (OMAP54XX_L4_PER_BASE + 0x6c000)
69 #define UART3_BASE              (OMAP54XX_L4_PER_BASE + 0x20000)
71 /* General Purpose Timers */
72 #define GPT1_BASE               (OMAP54XX_L4_WKUP_BASE + 0x18000)
73 #define GPT2_BASE               (OMAP54XX_L4_PER_BASE  + 0x32000)
74 #define GPT3_BASE               (OMAP54XX_L4_PER_BASE  + 0x34000)
76 /* Watchdog Timer2 - MPU watchdog */
77 #define WDT2_BASE               (OMAP54XX_L4_WKUP_BASE + 0x14000)
79 /* 32KTIMER */
80 #define SYNC_32KTIMER_BASE      (OMAP54XX_L4_WKUP_BASE + 0x4000)
82 /* GPMC */
83 #define OMAP54XX_GPMC_BASE      0x50000000
85 /* SYSTEM CONTROL MODULE */
86 #define SYSCTRL_GENERAL_CORE_BASE       0x4A002000
88 /*
89  * Hardware Register Details
90  */
92 /* Watchdog Timer */
93 #define WD_UNLOCK1              0xAAAA
94 #define WD_UNLOCK2              0x5555
96 /* GP Timer */
97 #define TCLR_ST                 (0x1 << 0)
98 #define TCLR_AR                 (0x1 << 1)
99 #define TCLR_PRE                (0x1 << 5)
101 /* Control Module */
102 #define LDOSRAM_ACTMODE_VSET_IN_MASK    (0x1F << 5)
103 #define LDOSRAM_VOLT_CTRL_OVERRIDE      0x0401040f
104 #define CONTROL_EFUSE_1_OVERRIDE        0x1C4D0110
105 #define CONTROL_EFUSE_2_OVERRIDE        0x00084000
107 /* LPDDR2 IO regs */
108 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN      0x1C1C1C1C
109 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER    0x9E9E9E9E
110 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN     0x7C7C7C7C
111 #define LPDDR2IO_GR10_WD_MASK                           (3 << 17)
112 #define CONTROL_LPDDR2IO_3_VAL          0xA0888C00
114 /* CONTROL_EFUSE_2 */
115 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1            0x00ffc000
117 #define SDCARD_PWRDNZ                                   (1 << 26)
118 #define SDCARD_BIAS_HIZ_MODE                            (1 << 25)
119 #define SDCARD_BIAS_PWRDNZ                              (1 << 22)
120 #define SDCARD_PBIASLITE_VMODE                          (1 << 21)
122 #ifndef __ASSEMBLY__
124 struct s32ktimer {
125         unsigned char res[0x10];
126         unsigned int s32k_cr;   /* 0x10 */
127 };
129 #define DEVICE_TYPE_SHIFT 0x6
130 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
131 #define DEVICE_GP 0x3
133 struct omap_sys_ctrl_regs {
134         u32 pad0[77]; /* 0x4A002000 */
135         u32 control_status; /* 0x4A002134 */
136         u32 pad1[794]; /* 0x4A002138 */
137         u32 control_paconf_global; /* 0x4A002DA0 */
138         u32 control_paconf_mode;  /* 0x4A002DA4 */
139         u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
140         u32 control_smart1io_padconf_1; /* 0x4A002DAC */
141         u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
142         u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
143         u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
144         u32 control_smart2io_padconf_2; /* 0x4A002DBC */
145         u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
146         u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
147         u32 pad2[14];
148         u32 control_pbias; /* 0x4A002E00 */
149         u32 control_i2c_0; /* 0x4A002E04 */
150         u32 control_camera_rx; /* 0x4A002E08 */
151         u32 control_hdmi_tx_phy; /* 0x4A002E0C */
152         u32 control_uniportm; /* 0x4A002E10 */
153         u32 control_dsiphy; /* 0x4A002E14 */
154         u32 control_mcbsplp; /* 0x4A002E18 */
155         u32 control_usb2phycore; /* 0x4A002E1C */
156         u32 control_hdmi_1; /*0x4A002E20*/
157         u32 control_hsi; /*0x4A002E24*/
158         u32 pad3[2];
159         u32 control_ddr3ch1_0; /*0x4A002E30*/
160         u32 control_ddr3ch2_0; /*0x4A002E34*/
161         u32 control_ddrch1_0;   /*0x4A002E38*/
162         u32 control_ddrch1_1;   /*0x4A002E3C*/
163         u32 control_ddrch2_0;   /*0x4A002E40*/
164         u32 control_ddrch2_1;   /*0x4A002E44*/
165         u32 control_lpddr2ch1_0; /*0x4A002E48*/
166         u32 control_lpddr2ch1_1; /*0x4A002E4C*/
167         u32 control_ddrio_0;  /*0x4A002E50*/
168         u32 control_ddrio_1;  /*0x4A002E54*/
169         u32 control_ddrio_2;  /*0x4A002E58*/
170         u32 control_hyst_1; /*0x4A002E5C*/
171         u32 control_usbb_hsic_control; /*0x4A002E60*/
172         u32 control_c2c; /*0x4A002E64*/
173         u32 control_core_control_spare_rw; /*0x4A002E68*/
174         u32 control_core_control_spare_r; /*0x4A002E6C*/
175         u32 control_core_control_spare_r_c0; /*0x4A002E70*/
176         u32 control_srcomp_north_side; /*0x4A002E74*/
177         u32 control_srcomp_south_side; /*0x4A002E78*/
178         u32 control_srcomp_east_side; /*0x4A002E7C*/
179         u32 control_srcomp_west_side; /*0x4A002E80*/
180         u32 control_srcomp_code_latch; /*0x4A002E84*/
181         u32 pad4[3680198];
182         u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
183         u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
184         u32 control_padconf_mode; /* 0x4AE0CDA8 */
185         u32 control_xtal_oscillator; /* 0x4AE0CDAC */
186         u32 control_i2c_2; /* 0x4AE0CDB0 */
187         u32 control_ckobuffer; /* 0x4AE0CDB4 */
188         u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
189         u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
190         u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
191         u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
192         u32 control_efuse_1; /* 0x4AE0CDC8 */
193         u32 control_efuse_2; /* 0x4AE0CDCC */
194         u32 control_efuse_3; /* 0x4AE0CDD0 */
195         u32 control_efuse_4; /* 0x4AE0CDD4 */
196         u32 control_efuse_5; /* 0x4AE0CDD8 */
197         u32 control_efuse_6; /* 0x4AE0CDDC */
198         u32 control_efuse_7; /* 0x4AE0CDE0 */
199         u32 control_efuse_8; /* 0x4AE0CDE4 */
200         u32 control_efuse_9; /* 0x4AE0CDE8 */
201         u32 control_efuse_10; /* 0x4AE0CDEC */
202         u32 control_efuse_11; /* 0x4AE0CDF0 */
203         u32 control_efuse_12; /* 0x4AE0CDF4 */
204         u32 control_efuse_13; /* 0x4AE0CDF8 */
205 };
207 /* Output impedance control */
208 #define ds_120_ohm      0x0
209 #define ds_60_ohm       0x1
210 #define ds_45_ohm       0x2
211 #define ds_30_ohm       0x3
212 #define ds_mask         0x3
214 /* Slew rate control */
215 #define sc_slow         0x0
216 #define sc_medium       0x1
217 #define sc_fast         0x2
218 #define sc_na           0x3
219 #define sc_mask         0x3
221 /* Target capacitance control */
222 #define lb_5_12_pf      0x0
223 #define lb_12_25_pf     0x1
224 #define lb_25_50_pf     0x2
225 #define lb_50_80_pf     0x3
226 #define lb_mask         0x3
228 #define usb_i_mask      0x7
230 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
231 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
232 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
233 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
234 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
236 #define EFUSE_1 0x45145100
237 #define EFUSE_2 0x45145100
238 #define EFUSE_3 0x45145100
239 #define EFUSE_4 0x45145100
240 #endif /* __ASSEMBLY__ */
242 /*
243  * Non-secure SRAM Addresses
244  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
245  * at 0x40304000(EMU base) so that our code works for both EMU and GP
246  */
247 #define NON_SECURE_SRAM_START   0x40300000
248 #define NON_SECURE_SRAM_END     0x40320000      /* Not inclusive */
249 /* base address for indirect vectors (internal boot mode) */
250 #define SRAM_ROM_VECT_BASE      0x4031F000
251 /* Temporary SRAM stack used while low level init is done */
252 #define LOW_LEVEL_SRAM_STACK    NON_SECURE_SRAM_END
254 #define SRAM_SCRATCH_SPACE_ADDR         NON_SECURE_SRAM_START
255 /*
256  * SRAM scratch space entries
257  */
258 #define OMAP5_SRAM_SCRATCH_OMAP5_REV    SRAM_SCRATCH_SPACE_ADDR
259 #define OMAP5_SRAM_SCRATCH_EMIF_SIZE    (SRAM_SCRATCH_SPACE_ADDR + 0x4)
260 #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM   (SRAM_SCRATCH_SPACE_ADDR + 0xC)
261 #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN   (SRAM_SCRATCH_SPACE_ADDR + 0x10)
262 #define OMAP5_SRAM_SCRATCH_SPACE_END    (SRAM_SCRATCH_SPACE_ADDR + 0x14)
264 /* Silicon revisions */
265 #define OMAP4430_SILICON_ID_INVALID     0xFFFFFFFF
266 #define OMAP4430_ES1_0  0x44300100
267 #define OMAP4430_ES2_0  0x44300200
268 #define OMAP4430_ES2_1  0x44300210
269 #define OMAP4430_ES2_2  0x44300220
270 #define OMAP4430_ES2_3  0x44300230
271 #define OMAP4460_ES1_0  0x44600100
272 #define OMAP4460_ES1_1  0x44600110
274 /* ROM code defines */
275 /* Boot device */
276 #define BOOT_DEVICE_MASK        0xFF
277 #define BOOT_DEVICE_OFFSET      0x8
278 #define DEV_DESC_PTR_OFFSET     0x4
279 #define DEV_DATA_PTR_OFFSET     0x18
280 #define BOOT_MODE_OFFSET        0x8
281 #define RESET_REASON_OFFSET     0x9
282 #define CH_FLAGS_OFFSET         0xA
284 #define CH_FLAGS_CHSETTINGS     (0x1 << 0)
285 #define CH_FLAGS_CHRAM          (0x1 << 1)
286 #define CH_FLAGS_CHFLASH        (0x1 << 2)
287 #define CH_FLAGS_CHMMCSD        (0x1 << 3)
289 #ifndef __ASSEMBLY__
290 struct omap_boot_parameters {
291         char *boot_message;
292         unsigned int mem_boot_descriptor;
293         unsigned char omap_bootdevice;
294         unsigned char reset_reason;
295         unsigned char ch_flags;
296 };
297 #endif /* __ASSEMBLY__ */
298 #endif