1 /*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 #include <common.h>
25 #include <command.h>
26 #include <netdev.h>
27 #include <asm/mipsregs.h>
28 #include <asm/cacheops.h>
29 #include <asm/reboot.h>
31 #define cache_op(op,addr) \
32 __asm__ __volatile__( \
33 " .set push \n" \
34 " .set noreorder \n" \
35 " .set mips3\n\t \n" \
36 " cache %0, %1 \n" \
37 " .set pop \n" \
38 : \
39 : "i" (op), "R" (*(unsigned char *)(addr)))
41 void __attribute__((weak)) _machine_restart(void)
42 {
43 }
45 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
46 {
47 _machine_restart();
49 fprintf(stderr, "*** reset failed ***\n");
50 return 0;
51 }
53 void flush_cache(ulong start_addr, ulong size)
54 {
55 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
56 unsigned long addr = start_addr & ~(lsize - 1);
57 unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
59 /* aend will be miscalculated when size is zero, so we return here */
60 if (size == 0)
61 return;
63 while (1) {
64 cache_op(HIT_WRITEBACK_INV_D, addr);
65 cache_op(HIT_INVALIDATE_I, addr);
66 if (addr == aend)
67 break;
68 addr += lsize;
69 }
70 }
72 void flush_dcache_range(ulong start_addr, ulong stop)
73 {
74 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
75 unsigned long addr = start_addr & ~(lsize - 1);
76 unsigned long aend = (stop - 1) & ~(lsize - 1);
78 while (1) {
79 cache_op(HIT_WRITEBACK_INV_D, addr);
80 if (addr == aend)
81 break;
82 addr += lsize;
83 }
84 }
86 void invalidate_dcache_range(ulong start_addr, ulong stop)
87 {
88 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
89 unsigned long addr = start_addr & ~(lsize - 1);
90 unsigned long aend = (stop - 1) & ~(lsize - 1);
92 while (1) {
93 cache_op(HIT_INVALIDATE_D, addr);
94 if (addr == aend)
95 break;
96 addr += lsize;
97 }
98 }
100 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
101 {
102 write_c0_entrylo0(low0);
103 write_c0_pagemask(pagemask);
104 write_c0_entrylo1(low1);
105 write_c0_entryhi(hi);
106 write_c0_index(index);
107 tlb_write_indexed();
108 }
110 int cpu_eth_init(bd_t *bis)
111 {
112 #ifdef CONFIG_SOC_AU1X00
113 au1x00_enet_initialize(bis);
114 #endif
115 return 0;
116 }