1 /*
2 * Startup Code for MIPS32 CPU-core
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
25 #include <asm-offsets.h>
26 #include <config.h>
27 #include <asm/regdef.h>
28 #include <asm/mipsregs.h>
30 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
31 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
32 #endif
34 /*
35 * For the moment disable interrupts, mark the kernel mode and
36 * set ST0_KX so that the CPU does not spit fire when using
37 * 64-bit addresses.
38 */
39 .macro setup_c0_status set clr
40 .set push
41 mfc0 t0, CP0_STATUS
42 or t0, ST0_CU0 | \set | 0x1f | \clr
43 xor t0, 0x1f | \clr
44 mtc0 t0, CP0_STATUS
45 .set noreorder
46 sll zero, 3 # ehb
47 .set pop
48 .endm
50 .set noreorder
52 .globl _start
53 .text
54 _start:
55 /* U-boot entry point */
56 b reset
57 nop
59 .org 0x10
60 #ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
61 /*
62 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
63 * access external NOR flashes. If the board boots from NOR flash the
64 * internal BootROM does a blind read at address 0xB0000010 to read the
65 * initial configuration for that EBU in order to access the flash
66 * device with correct parameters. This config option is board-specific.
67 */
68 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
69 .word 0x0
70 #endif
72 .org 0x200
73 /* TLB refill, 32 bit task */
74 1: b 1b
75 nop
77 .org 0x280
78 /* XTLB refill, 64 bit task */
79 1: b 1b
80 nop
82 .org 0x300
83 /* Cache error exception */
84 1: b 1b
85 nop
87 .org 0x380
88 /* General exception */
89 1: b 1b
90 nop
92 .org 0x400
93 /* Catch interrupt exceptions */
94 1: b 1b
95 nop
97 .org 0x480
98 /* EJTAG debug exception */
99 1: b 1b
100 nop
102 .align 4
103 reset:
105 /* Clear watch registers */
106 mtc0 zero, CP0_WATCHLO
107 mtc0 zero, CP0_WATCHHI
109 /* WP(Watch Pending), SW0/1 should be cleared */
110 mtc0 zero, CP0_CAUSE
112 setup_c0_status 0 0
114 /* Init Timer */
115 mtc0 zero, CP0_COUNT
116 mtc0 zero, CP0_COMPARE
118 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
119 /* CONFIG0 register */
120 li t0, CONF_CM_UNCACHED
121 mtc0 t0, CP0_CONFIG
122 #endif
124 /* Initialize $gp */
125 bal 1f
126 nop
127 .word _gp
128 1:
129 lw gp, 0(ra)
131 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
132 /* Initialize any external memory */
133 la t9, lowlevel_init
134 jalr t9
135 nop
137 /* Initialize caches... */
138 la t9, mips_cache_reset
139 jalr t9
140 nop
142 /* ... and enable them */
143 li t0, CONFIG_SYS_MIPS_CACHE_MODE
144 mtc0 t0, CP0_CONFIG
145 #endif
147 /* Set up temporary stack */
148 li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
150 la t9, board_init_f
151 jr t9
152 nop
154 /*
155 * void relocate_code (addr_sp, gd, addr_moni)
156 *
157 * This "function" does not return, instead it continues in RAM
158 * after relocating the monitor code.
159 *
160 * a0 = addr_sp
161 * a1 = gd
162 * a2 = destination address
163 */
164 .globl relocate_code
165 .ent relocate_code
166 relocate_code:
167 move sp, a0 # set new stack pointer
169 move s0, a1 # save gd in s0
170 move s2, a2 # save destination address in s2
172 li t0, CONFIG_SYS_MONITOR_BASE
173 sub s1, s2, t0 # s1 <-- relocation offset
175 la t3, in_ram
176 lw t2, -12(t3) # t2 <-- __image_copy_end
177 move t1, a2
179 add gp, s1 # adjust gp
181 /*
182 * t0 = source address
183 * t1 = target address
184 * t2 = source end address
185 */
186 1:
187 lw t3, 0(t0)
188 sw t3, 0(t1)
189 addu t0, 4
190 blt t0, t2, 1b
191 addu t1, 4
193 /* If caches were enabled, we would have to flush them here. */
194 sub a1, t1, s2 # a1 <-- size
195 la t9, flush_cache
196 jalr t9
197 move a0, s2 # a0 <-- destination address
199 /* Jump to where we've relocated ourselves */
200 addi t0, s2, in_ram - _start
201 jr t0
202 nop
204 .word __rel_dyn_end
205 .word __rel_dyn_start
206 .word __image_copy_end
207 .word _GLOBAL_OFFSET_TABLE_
208 .word num_got_entries
210 in_ram:
211 /*
212 * Now we want to update GOT.
213 *
214 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
215 * generated by GNU ld. Skip these reserved entries from relocation.
216 */
217 lw t3, -4(t0) # t3 <-- num_got_entries
218 lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
219 add t4, s1 # t4 now holds relocated _G_O_T_
220 addi t4, t4, 8 # skipping first two entries
221 li t2, 2
222 1:
223 lw t1, 0(t4)
224 beqz t1, 2f
225 add t1, s1
226 sw t1, 0(t4)
227 2:
228 addi t2, 1
229 blt t2, t3, 1b
230 addi t4, 4
232 /* Update dynamic relocations */
233 lw t1, -16(t0) # t1 <-- __rel_dyn_start
234 lw t2, -20(t0) # t2 <-- __rel_dyn_end
236 b 2f # skip first reserved entry
237 addi t1, 8
239 1:
240 lw t3, -4(t1) # t3 <-- relocation info
242 sub t3, 3
243 bnez t3, 2f # skip non R_MIPS_REL32 entries
244 nop
246 lw t3, -8(t1) # t3 <-- location to fix up in FLASH
248 lw t4, 0(t3) # t4 <-- original pointer
249 add t4, s1 # t4 <-- adjusted pointer
251 add t3, s1 # t3 <-- location to fix up in RAM
252 sw t4, 0(t3)
254 2:
255 blt t1, t2, 1b
256 addi t1, 8 # each rel.dyn entry is 8 bytes
258 /*
259 * Clear BSS
260 *
261 * GOT is now relocated. Thus __bss_start and __bss_end can be
262 * accessed directly via $gp.
263 */
264 la t1, __bss_start # t1 <-- __bss_start
265 la t2, __bss_end # t2 <-- __bss_end
267 1:
268 sw zero, 0(t1)
269 blt t1, t2, 1b
270 addi t1, 4
272 move a0, s0 # a0 <-- gd
273 la t9, board_init_r
274 jr t9
275 move a1, s2
277 .end relocate_code