Merge branch 'next'
[glsdk/glsdk-u-boot.git] / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c
1 /*
2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License as published by the Free
6  * Software Foundation; either version 2 of the License, or (at your option)
7  * any later version.
8  */
10 /*
11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12  * Based on code from spd_sdram.c
13  * Author: James Yang [at freescale.com]
14  */
16 #include <common.h>
17 #include <asm/fsl_ddr_sdram.h>
19 #include "ddr.h"
21 #ifdef CONFIG_MPC83xx
22         #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
23 #elif defined(CONFIG_MPC85xx)
24         #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
25 #elif defined(CONFIG_MPC86xx)
26         #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
27 #else
28         #error "Undefined _DDR_ADDR"
29 #endif
31 u32 fsl_ddr_get_version(void)
32 {
33         ccsr_ddr_t *ddr;
34         u32 ver_major_minor_errata;
36         ddr = (void *)_DDR_ADDR;
37         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
38         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
40         return ver_major_minor_errata;
41 }
43 unsigned int picos_to_mclk(unsigned int picos);
45 /*
46  * Determine Rtt value.
47  *
48  * This should likely be either board or controller specific.
49  *
50  * Rtt(nominal) - DDR2:
51  *      0 = Rtt disabled
52  *      1 = 75 ohm
53  *      2 = 150 ohm
54  *      3 = 50 ohm
55  * Rtt(nominal) - DDR3:
56  *      0 = Rtt disabled
57  *      1 = 60 ohm
58  *      2 = 120 ohm
59  *      3 = 40 ohm
60  *      4 = 20 ohm
61  *      5 = 30 ohm
62  *
63  * FIXME: Apparently 8641 needs a value of 2
64  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
65  *
66  * FIXME: There was some effort down this line earlier:
67  *
68  *      unsigned int i;
69  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
70  *              if (popts->dimmslot[i].num_valid_cs
71  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
72  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
73  *                      rtt = 2;
74  *                      break;
75  *              }
76  *      }
77  */
78 static inline int fsl_ddr_get_rtt(void)
79 {
80         int rtt;
82 #if defined(CONFIG_FSL_DDR1)
83         rtt = 0;
84 #elif defined(CONFIG_FSL_DDR2)
85         rtt = 3;
86 #else
87         rtt = 0;
88 #endif
90         return rtt;
91 }
93 /*
94  * compute the CAS write latency according to DDR3 spec
95  * CWL = 5 if tCK >= 2.5ns
96  *       6 if 2.5ns > tCK >= 1.875ns
97  *       7 if 1.875ns > tCK >= 1.5ns
98  *       8 if 1.5ns > tCK >= 1.25ns
99  *       9 if 1.25ns > tCK >= 1.07ns
100  *       10 if 1.07ns > tCK >= 0.935ns
101  *       11 if 0.935ns > tCK >= 0.833ns
102  *       12 if 0.833ns > tCK >= 0.75ns
103  */
104 static inline unsigned int compute_cas_write_latency(void)
106         unsigned int cwl;
107         const unsigned int mclk_ps = get_memory_clk_period_ps();
109         if (mclk_ps >= 2500)
110                 cwl = 5;
111         else if (mclk_ps >= 1875)
112                 cwl = 6;
113         else if (mclk_ps >= 1500)
114                 cwl = 7;
115         else if (mclk_ps >= 1250)
116                 cwl = 8;
117         else if (mclk_ps >= 1070)
118                 cwl = 9;
119         else if (mclk_ps >= 935)
120                 cwl = 10;
121         else if (mclk_ps >= 833)
122                 cwl = 11;
123         else if (mclk_ps >= 750)
124                 cwl = 12;
125         else {
126                 cwl = 12;
127                 printf("Warning: CWL is out of range\n");
128         }
129         return cwl;
132 /* Chip Select Configuration (CSn_CONFIG) */
133 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
134                                const memctl_options_t *popts,
135                                const dimm_params_t *dimm_params)
137         unsigned int cs_n_en = 0; /* Chip Select enable */
138         unsigned int intlv_en = 0; /* Memory controller interleave enable */
139         unsigned int intlv_ctl = 0; /* Interleaving control */
140         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
141         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
142         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
143         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
144         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
145         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
146         int go_config = 0;
148         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
149         switch (i) {
150         case 0:
151                 if (dimm_params[dimm_number].n_ranks > 0) {
152                         go_config = 1;
153                         /* These fields only available in CS0_CONFIG */
154                         if (!popts->memctl_interleaving)
155                                 break;
156                         switch (popts->memctl_interleaving_mode) {
157                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
158                         case FSL_DDR_PAGE_INTERLEAVING:
159                         case FSL_DDR_BANK_INTERLEAVING:
160                         case FSL_DDR_SUPERBANK_INTERLEAVING:
161                                 intlv_en = popts->memctl_interleaving;
162                                 intlv_ctl = popts->memctl_interleaving_mode;
163                                 break;
164                         default:
165                                 break;
166                         }
167                 }
168                 break;
169         case 1:
170                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
171                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
172                         go_config = 1;
173                 break;
174         case 2:
175                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
176                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
177                         go_config = 1;
178                 break;
179         case 3:
180                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
181                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
182                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
183                         go_config = 1;
184                 break;
185         default:
186                 break;
187         }
188         if (go_config) {
189                 unsigned int n_banks_per_sdram_device;
190                 cs_n_en = 1;
191                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
192                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
193                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
194                 n_banks_per_sdram_device
195                         = dimm_params[dimm_number].n_banks_per_sdram_device;
196                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
197                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
198                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
199         }
200         ddr->cs[i].config = (0
201                 | ((cs_n_en & 0x1) << 31)
202                 | ((intlv_en & 0x3) << 29)
203                 | ((intlv_ctl & 0xf) << 24)
204                 | ((ap_n_en & 0x1) << 23)
206                 /* XXX: some implementation only have 1 bit starting at left */
207                 | ((odt_rd_cfg & 0x7) << 20)
209                 /* XXX: Some implementation only have 1 bit starting at left */
210                 | ((odt_wr_cfg & 0x7) << 16)
212                 | ((ba_bits_cs_n & 0x3) << 14)
213                 | ((row_bits_cs_n & 0x7) << 8)
214                 | ((col_bits_cs_n & 0x7) << 0)
215                 );
216         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
219 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
220 /* FIXME: 8572 */
221 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
223         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
225         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
226         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
229 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
231 #if !defined(CONFIG_FSL_DDR1)
232 /*
233  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
234  *
235  * Avoid writing for DDR I.  The new PQ38 DDR controller
236  * dreams up non-zero default values to be backwards compatible.
237  */
238 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
239                                 const memctl_options_t *popts)
241         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
242         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
243         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
244         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
245         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
247         /* Active powerdown exit timing (tXARD and tXARDS). */
248         unsigned char act_pd_exit_mclk;
249         /* Precharge powerdown exit timing (tXP). */
250         unsigned char pre_pd_exit_mclk;
251         /* ODT powerdown exit timing (tAXPD). */
252         unsigned char taxpd_mclk;
253         /* Mode register set cycle time (tMRD). */
254         unsigned char tmrd_mclk;
256 #ifdef CONFIG_FSL_DDR3
257         /*
258          * (tXARD and tXARDS). Empirical?
259          * The DDR3 spec has not tXARD,
260          * we use the tXP instead of it.
261          * tXP=max(3nCK, 7.5ns) for DDR3.
262          * spec has not the tAXPD, we use
263          * tAXPD=1, need design to confirm.
264          */
265         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
266         unsigned int data_rate = get_ddr_freq(0);
267         tmrd_mclk = 4;
268         /* set the turnaround time */
269         trwt_mclk = 1;
270         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
271                 twrt_mclk = 1;
273         if (popts->dynamic_power == 0) {        /* powerdown is not used */
274                 act_pd_exit_mclk = 1;
275                 pre_pd_exit_mclk = 1;
276                 taxpd_mclk = 1;
277         } else {
278                 /* act_pd_exit_mclk = tXARD, see above */
279                 act_pd_exit_mclk = picos_to_mclk(tXP);
280                 /* Mode register MR0[A12] is '1' - fast exit */
281                 pre_pd_exit_mclk = act_pd_exit_mclk;
282                 taxpd_mclk = 1;
283         }
284 #else /* CONFIG_FSL_DDR2 */
285         /*
286          * (tXARD and tXARDS). Empirical?
287          * tXARD = 2 for DDR2
288          * tXP=2
289          * tAXPD=8
290          */
291         act_pd_exit_mclk = 2;
292         pre_pd_exit_mclk = 2;
293         taxpd_mclk = 8;
294         tmrd_mclk = 2;
295 #endif
297         if (popts->trwt_override)
298                 trwt_mclk = popts->trwt;
300         ddr->timing_cfg_0 = (0
301                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
302                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
303                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
304                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
305                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
306                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
307                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
308                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
309                 );
310         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
312 #endif  /* defined(CONFIG_FSL_DDR2) */
314 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
315 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
316                                const memctl_options_t *popts,
317                                const common_timing_params_t *common_dimm,
318                                unsigned int cas_latency)
320         /* Extended precharge to activate interval (tRP) */
321         unsigned int ext_pretoact = 0;
322         /* Extended Activate to precharge interval (tRAS) */
323         unsigned int ext_acttopre = 0;
324         /* Extended activate to read/write interval (tRCD) */
325         unsigned int ext_acttorw = 0;
326         /* Extended refresh recovery time (tRFC) */
327         unsigned int ext_refrec;
328         /* Extended MCAS latency from READ cmd */
329         unsigned int ext_caslat = 0;
330         /* Extended last data to precharge interval (tWR) */
331         unsigned int ext_wrrec = 0;
332         /* Control Adjust */
333         unsigned int cntl_adj = 0;
335         ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
336         ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
337         ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
338         ext_caslat = (2 * cas_latency - 1) >> 4;
339         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
340         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
341         ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
342                 (popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
344         ddr->timing_cfg_3 = (0
345                 | ((ext_pretoact & 0x1) << 28)
346                 | ((ext_acttopre & 0x2) << 24)
347                 | ((ext_acttorw & 0x1) << 22)
348                 | ((ext_refrec & 0x1F) << 16)
349                 | ((ext_caslat & 0x3) << 12)
350                 | ((ext_wrrec & 0x1) << 8)
351                 | ((cntl_adj & 0x7) << 0)
352                 );
353         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
356 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
357 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
358                                const memctl_options_t *popts,
359                                const common_timing_params_t *common_dimm,
360                                unsigned int cas_latency)
362         /* Precharge-to-activate interval (tRP) */
363         unsigned char pretoact_mclk;
364         /* Activate to precharge interval (tRAS) */
365         unsigned char acttopre_mclk;
366         /*  Activate to read/write interval (tRCD) */
367         unsigned char acttorw_mclk;
368         /* CASLAT */
369         unsigned char caslat_ctrl;
370         /*  Refresh recovery time (tRFC) ; trfc_low */
371         unsigned char refrec_ctrl;
372         /* Last data to precharge minimum interval (tWR) */
373         unsigned char wrrec_mclk;
374         /* Activate-to-activate interval (tRRD) */
375         unsigned char acttoact_mclk;
376         /* Last write data pair to read command issue interval (tWTR) */
377         unsigned char wrtord_mclk;
378         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
379         static const u8 wrrec_table[] = {
380                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
382         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
383         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
384         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
386         /*
387          * Translate CAS Latency to a DDR controller field value:
388          *
389          *      CAS Lat DDR I   DDR II  Ctrl
390          *      Clocks  SPD Bit SPD Bit Value
391          *      ------- ------- ------- -----
392          *      1.0     0               0001
393          *      1.5     1               0010
394          *      2.0     2       2       0011
395          *      2.5     3               0100
396          *      3.0     4       3       0101
397          *      3.5     5               0110
398          *      4.0             4       0111
399          *      4.5                     1000
400          *      5.0             5       1001
401          */
402 #if defined(CONFIG_FSL_DDR1)
403         caslat_ctrl = (cas_latency + 1) & 0x07;
404 #elif defined(CONFIG_FSL_DDR2)
405         caslat_ctrl = 2 * cas_latency - 1;
406 #else
407         /*
408          * if the CAS latency more than 8 cycle,
409          * we need set extend bit for it at
410          * TIMING_CFG_3[EXT_CASLAT]
411          */
412         caslat_ctrl = 2 * cas_latency - 1;
413 #endif
415         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
416         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
418         if (wrrec_mclk > 16)
419                 printf("Error: WRREC doesn't support more than 16 clocks\n");
420         else
421                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
422         if (popts->OTF_burst_chop_en)
423                 wrrec_mclk += 2;
425         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
426         /*
427          * JEDEC has min requirement for tRRD
428          */
429 #if defined(CONFIG_FSL_DDR3)
430         if (acttoact_mclk < 4)
431                 acttoact_mclk = 4;
432 #endif
433         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
434         /*
435          * JEDEC has some min requirements for tWTR
436          */
437 #if defined(CONFIG_FSL_DDR2)
438         if (wrtord_mclk < 2)
439                 wrtord_mclk = 2;
440 #elif defined(CONFIG_FSL_DDR3)
441         if (wrtord_mclk < 4)
442                 wrtord_mclk = 4;
443 #endif
444         if (popts->OTF_burst_chop_en)
445                 wrtord_mclk += 2;
447         ddr->timing_cfg_1 = (0
448                 | ((pretoact_mclk & 0x0F) << 28)
449                 | ((acttopre_mclk & 0x0F) << 24)
450                 | ((acttorw_mclk & 0xF) << 20)
451                 | ((caslat_ctrl & 0xF) << 16)
452                 | ((refrec_ctrl & 0xF) << 12)
453                 | ((wrrec_mclk & 0x0F) << 8)
454                 | ((acttoact_mclk & 0x07) << 4)
455                 | ((wrtord_mclk & 0x07) << 0)
456                 );
457         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
460 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
461 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
462                                const memctl_options_t *popts,
463                                const common_timing_params_t *common_dimm,
464                                unsigned int cas_latency,
465                                unsigned int additive_latency)
467         /* Additive latency */
468         unsigned char add_lat_mclk;
469         /* CAS-to-preamble override */
470         unsigned short cpo;
471         /* Write latency */
472         unsigned char wr_lat;
473         /*  Read to precharge (tRTP) */
474         unsigned char rd_to_pre;
475         /* Write command to write data strobe timing adjustment */
476         unsigned char wr_data_delay;
477         /* Minimum CKE pulse width (tCKE) */
478         unsigned char cke_pls;
479         /* Window for four activates (tFAW) */
480         unsigned short four_act;
482         /* FIXME add check that this must be less than acttorw_mclk */
483         add_lat_mclk = additive_latency;
484         cpo = popts->cpo_override;
486 #if defined(CONFIG_FSL_DDR1)
487         /*
488          * This is a lie.  It should really be 1, but if it is
489          * set to 1, bits overlap into the old controller's
490          * otherwise unused ACSM field.  If we leave it 0, then
491          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
492          */
493         wr_lat = 0;
494 #elif defined(CONFIG_FSL_DDR2)
495         wr_lat = cas_latency - 1;
496 #else
497         wr_lat = compute_cas_write_latency();
498 #endif
500         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
501         /*
502          * JEDEC has some min requirements for tRTP
503          */
504 #if defined(CONFIG_FSL_DDR2)
505         if (rd_to_pre  < 2)
506                 rd_to_pre  = 2;
507 #elif defined(CONFIG_FSL_DDR3)
508         if (rd_to_pre < 4)
509                 rd_to_pre = 4;
510 #endif
511         if (additive_latency)
512                 rd_to_pre += additive_latency;
513         if (popts->OTF_burst_chop_en)
514                 rd_to_pre += 2; /* according to UM */
516         wr_data_delay = popts->write_data_delay;
517         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
518         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
520         ddr->timing_cfg_2 = (0
521                 | ((add_lat_mclk & 0xf) << 28)
522                 | ((cpo & 0x1f) << 23)
523                 | ((wr_lat & 0xf) << 19)
524                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
525                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
526                 | ((cke_pls & 0x7) << 6)
527                 | ((four_act & 0x3f) << 0)
528                 );
529         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
532 /* DDR SDRAM Register Control Word */
533 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
534                                const memctl_options_t *popts,
535                                const common_timing_params_t *common_dimm)
537         if (common_dimm->all_DIMMs_registered
538                 && !common_dimm->all_DIMMs_unbuffered) {
539                 if (popts->rcw_override) {
540                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
541                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
542                 } else {
543                         ddr->ddr_sdram_rcw_1 =
544                                 common_dimm->rcw[0] << 28 | \
545                                 common_dimm->rcw[1] << 24 | \
546                                 common_dimm->rcw[2] << 20 | \
547                                 common_dimm->rcw[3] << 16 | \
548                                 common_dimm->rcw[4] << 12 | \
549                                 common_dimm->rcw[5] << 8 | \
550                                 common_dimm->rcw[6] << 4 | \
551                                 common_dimm->rcw[7];
552                         ddr->ddr_sdram_rcw_2 =
553                                 common_dimm->rcw[8] << 28 | \
554                                 common_dimm->rcw[9] << 24 | \
555                                 common_dimm->rcw[10] << 20 | \
556                                 common_dimm->rcw[11] << 16 | \
557                                 common_dimm->rcw[12] << 12 | \
558                                 common_dimm->rcw[13] << 8 | \
559                                 common_dimm->rcw[14] << 4 | \
560                                 common_dimm->rcw[15];
561                 }
562                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
563                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
564         }
567 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
568 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
569                                const memctl_options_t *popts,
570                                const common_timing_params_t *common_dimm)
572         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
573         unsigned int sren;              /* Self refresh enable (during sleep) */
574         unsigned int ecc_en;            /* ECC enable. */
575         unsigned int rd_en;             /* Registered DIMM enable */
576         unsigned int sdram_type;        /* Type of SDRAM */
577         unsigned int dyn_pwr;           /* Dynamic power management mode */
578         unsigned int dbw;               /* DRAM dta bus width */
579         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
580         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
581         unsigned int threeT_en;         /* Enable 3T timing */
582         unsigned int twoT_en;           /* Enable 2T timing */
583         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
584         unsigned int x32_en = 0;        /* x32 enable */
585         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
586         unsigned int hse;               /* Global half strength override */
587         unsigned int mem_halt = 0;      /* memory controller halt */
588         unsigned int bi = 0;            /* Bypass initialization */
590         mem_en = 1;
591         sren = popts->self_refresh_in_sleep;
592         if (common_dimm->all_DIMMs_ECC_capable) {
593                 /* Allow setting of ECC only if all DIMMs are ECC. */
594                 ecc_en = popts->ECC_mode;
595         } else {
596                 ecc_en = 0;
597         }
599         if (common_dimm->all_DIMMs_registered
600                 && !common_dimm->all_DIMMs_unbuffered) {
601                 rd_en = 1;
602                 twoT_en = 0;
603         } else {
604                 rd_en = 0;
605                 twoT_en = popts->twoT_en;
606         }
608         sdram_type = CONFIG_FSL_SDRAM_TYPE;
610         dyn_pwr = popts->dynamic_power;
611         dbw = popts->data_bus_width;
612         /* 8-beat burst enable DDR-III case
613          * we must clear it when use the on-the-fly mode,
614          * must set it when use the 32-bits bus mode.
615          */
616         if (sdram_type == SDRAM_TYPE_DDR3) {
617                 if (popts->burst_length == DDR_BL8)
618                         eight_be = 1;
619                 if (popts->burst_length == DDR_OTF)
620                         eight_be = 0;
621                 if (dbw == 0x1)
622                         eight_be = 1;
623         }
625         threeT_en = popts->threeT_en;
626         ba_intlv_ctl = popts->ba_intlv_ctl;
627         hse = popts->half_strength_driver_enable;
629         ddr->ddr_sdram_cfg = (0
630                         | ((mem_en & 0x1) << 31)
631                         | ((sren & 0x1) << 30)
632                         | ((ecc_en & 0x1) << 29)
633                         | ((rd_en & 0x1) << 28)
634                         | ((sdram_type & 0x7) << 24)
635                         | ((dyn_pwr & 0x1) << 21)
636                         | ((dbw & 0x3) << 19)
637                         | ((eight_be & 0x1) << 18)
638                         | ((ncap & 0x1) << 17)
639                         | ((threeT_en & 0x1) << 16)
640                         | ((twoT_en & 0x1) << 15)
641                         | ((ba_intlv_ctl & 0x7F) << 8)
642                         | ((x32_en & 0x1) << 5)
643                         | ((pchb8 & 0x1) << 4)
644                         | ((hse & 0x1) << 3)
645                         | ((mem_halt & 0x1) << 1)
646                         | ((bi & 0x1) << 0)
647                         );
648         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
651 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
652 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
653                                const memctl_options_t *popts,
654                                const unsigned int unq_mrs_en)
656         unsigned int frc_sr = 0;        /* Force self refresh */
657         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
658         unsigned int dll_rst_dis;       /* DLL reset disable */
659         unsigned int dqs_cfg;           /* DQS configuration */
660         unsigned int odt_cfg = 0;       /* ODT configuration */
661         unsigned int num_pr;            /* Number of posted refreshes */
662         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
663         unsigned int ap_en;             /* Address Parity Enable */
664         unsigned int d_init;            /* DRAM data initialization */
665         unsigned int rcw_en = 0;        /* Register Control Word Enable */
666         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
667         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
668         int i;
670         dll_rst_dis = 1;        /* Make this configurable */
671         dqs_cfg = popts->DQS_config;
672         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
673                 if (popts->cs_local_opts[i].odt_rd_cfg
674                         || popts->cs_local_opts[i].odt_wr_cfg) {
675                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
676                         break;
677                 }
678         }
680         num_pr = 1;     /* Make this configurable */
682         /*
683          * 8572 manual says
684          *     {TIMING_CFG_1[PRETOACT]
685          *      + [DDR_SDRAM_CFG_2[NUM_PR]
686          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
687          *      << DDR_SDRAM_INTERVAL[REFINT]
688          */
689 #if defined(CONFIG_FSL_DDR3)
690         obc_cfg = popts->OTF_burst_chop_en;
691 #else
692         obc_cfg = 0;
693 #endif
695         if (popts->registered_dimm_en) {
696                 rcw_en = 1;
697                 ap_en = popts->ap_en;
698         } else {
699                 ap_en = 0;
700         }
702 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
703         /* Use the DDR controller to auto initialize memory. */
704         d_init = popts->ECC_init_using_memctl;
705         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
706         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
707 #else
708         /* Memory will be initialized via DMA, or not at all. */
709         d_init = 0;
710 #endif
712 #if defined(CONFIG_FSL_DDR3)
713         md_en = popts->mirrored_dimm;
714 #endif
715         qd_en = popts->quad_rank_present ? 1 : 0;
716         ddr->ddr_sdram_cfg_2 = (0
717                 | ((frc_sr & 0x1) << 31)
718                 | ((sr_ie & 0x1) << 30)
719                 | ((dll_rst_dis & 0x1) << 29)
720                 | ((dqs_cfg & 0x3) << 26)
721                 | ((odt_cfg & 0x3) << 21)
722                 | ((num_pr & 0xf) << 12)
723                 | (qd_en << 9)
724                 | (unq_mrs_en << 8)
725                 | ((obc_cfg & 0x1) << 6)
726                 | ((ap_en & 0x1) << 5)
727                 | ((d_init & 0x1) << 4)
728                 | ((rcw_en & 0x1) << 2)
729                 | ((md_en & 0x1) << 0)
730                 );
731         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
734 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
735 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
736                                 const memctl_options_t *popts,
737                                 const unsigned int unq_mrs_en)
739         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
740         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
742 #if defined(CONFIG_FSL_DDR3)
743         int i;
744         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
745         unsigned int srt = 0;   /* self-refresh temerature, normal range */
746         unsigned int asr = 0;   /* auto self-refresh disable */
747         unsigned int cwl = compute_cas_write_latency() - 5;
748         unsigned int pasr = 0;  /* partial array self refresh disable */
750         if (popts->rtt_override)
751                 rtt_wr = popts->rtt_wr_override_value;
752         else
753                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
754         esdmode2 = (0
755                 | ((rtt_wr & 0x3) << 9)
756                 | ((srt & 0x1) << 7)
757                 | ((asr & 0x1) << 6)
758                 | ((cwl & 0x7) << 3)
759                 | ((pasr & 0x7) << 0));
760 #endif
761         ddr->ddr_sdram_mode_2 = (0
762                                  | ((esdmode2 & 0xFFFF) << 16)
763                                  | ((esdmode3 & 0xFFFF) << 0)
764                                  );
765         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
767 #ifdef CONFIG_FSL_DDR3
768         if (unq_mrs_en) {       /* unique mode registers are supported */
769                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
770                         if (popts->rtt_override)
771                                 rtt_wr = popts->rtt_wr_override_value;
772                         else
773                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
775                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
776                         esdmode2 |= (rtt_wr & 0x3) << 9;
777                         switch (i) {
778                         case 1:
779                                 ddr->ddr_sdram_mode_4 = (0
780                                         | ((esdmode2 & 0xFFFF) << 16)
781                                         | ((esdmode3 & 0xFFFF) << 0)
782                                         );
783                                 break;
784                         case 2:
785                                 ddr->ddr_sdram_mode_6 = (0
786                                         | ((esdmode2 & 0xFFFF) << 16)
787                                         | ((esdmode3 & 0xFFFF) << 0)
788                                         );
789                                 break;
790                         case 3:
791                                 ddr->ddr_sdram_mode_8 = (0
792                                         | ((esdmode2 & 0xFFFF) << 16)
793                                         | ((esdmode3 & 0xFFFF) << 0)
794                                         );
795                                 break;
796                         }
797                 }
798                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
799                         ddr->ddr_sdram_mode_4);
800                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
801                         ddr->ddr_sdram_mode_6);
802                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
803                         ddr->ddr_sdram_mode_8);
804         }
805 #endif
808 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
809 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
810                                const memctl_options_t *popts,
811                                const common_timing_params_t *common_dimm)
813         unsigned int refint;    /* Refresh interval */
814         unsigned int bstopre;   /* Precharge interval */
816         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
818         bstopre = popts->bstopre;
820         /* refint field used 0x3FFF in earlier controllers */
821         ddr->ddr_sdram_interval = (0
822                                    | ((refint & 0xFFFF) << 16)
823                                    | ((bstopre & 0x3FFF) << 0)
824                                    );
825         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
828 #if defined(CONFIG_FSL_DDR3)
829 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
830 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
831                                const memctl_options_t *popts,
832                                const common_timing_params_t *common_dimm,
833                                unsigned int cas_latency,
834                                unsigned int additive_latency,
835                                const unsigned int unq_mrs_en)
837         unsigned short esdmode;         /* Extended SDRAM mode */
838         unsigned short sdmode;          /* SDRAM mode */
840         /* Mode Register - MR1 */
841         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
842         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
843         unsigned int rtt;
844         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
845         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
846         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
847         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
848                                                        1=Disable (Test/Debug) */
850         /* Mode Register - MR0 */
851         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
852         unsigned int wr = 0;    /* Write Recovery */
853         unsigned int dll_rst;   /* DLL Reset */
854         unsigned int mode;      /* Normal=0 or Test=1 */
855         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
856         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
857         unsigned int bt;
858         unsigned int bl;        /* BL: Burst Length */
860         unsigned int wr_mclk;
861         /*
862          * DDR_SDRAM_MODE doesn't support 9,11,13,15
863          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
864          * for this table
865          */
866         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
868         const unsigned int mclk_ps = get_memory_clk_period_ps();
869         int i;
871         if (popts->rtt_override)
872                 rtt = popts->rtt_override_value;
873         else
874                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
876         if (additive_latency == (cas_latency - 1))
877                 al = 1;
878         if (additive_latency == (cas_latency - 2))
879                 al = 2;
881         if (popts->quad_rank_present)
882                 dic = 1;        /* output driver impedance 240/7 ohm */
884         /*
885          * The esdmode value will also be used for writing
886          * MR1 during write leveling for DDR3, although the
887          * bits specifically related to the write leveling
888          * scheme will be handled automatically by the DDR
889          * controller. so we set the wrlvl_en = 0 here.
890          */
891         esdmode = (0
892                 | ((qoff & 0x1) << 12)
893                 | ((tdqs_en & 0x1) << 11)
894                 | ((rtt & 0x4) << 7)   /* rtt field is split */
895                 | ((wrlvl_en & 0x1) << 7)
896                 | ((rtt & 0x2) << 5)   /* rtt field is split */
897                 | ((dic & 0x2) << 4)   /* DIC field is split */
898                 | ((al & 0x3) << 3)
899                 | ((rtt & 0x1) << 2)  /* rtt field is split */
900                 | ((dic & 0x1) << 1)   /* DIC field is split */
901                 | ((dll_en & 0x1) << 0)
902                 );
904         /*
905          * DLL control for precharge PD
906          * 0=slow exit DLL off (tXPDLL)
907          * 1=fast exit DLL on (tXP)
908          */
909         dll_on = 1;
911         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
912         if (wr_mclk <= 16) {
913                 wr = wr_table[wr_mclk - 5];
914         } else {
915                 printf("Error: unsupported write recovery for mode register "
916                        "wr_mclk = %d\n", wr_mclk);
917         }
919         dll_rst = 0;    /* dll no reset */
920         mode = 0;       /* normal mode */
922         /* look up table to get the cas latency bits */
923         if (cas_latency >= 5 && cas_latency <= 16) {
924                 unsigned char cas_latency_table[] = {
925                         0x2,    /* 5 clocks */
926                         0x4,    /* 6 clocks */
927                         0x6,    /* 7 clocks */
928                         0x8,    /* 8 clocks */
929                         0xa,    /* 9 clocks */
930                         0xc,    /* 10 clocks */
931                         0xe,    /* 11 clocks */
932                         0x1,    /* 12 clocks */
933                         0x3,    /* 13 clocks */
934                         0x5,    /* 14 clocks */
935                         0x7,    /* 15 clocks */
936                         0x9,    /* 16 clocks */
937                 };
938                 caslat = cas_latency_table[cas_latency - 5];
939         } else {
940                 printf("Error: unsupported cas latency for mode register\n");
941         }
943         bt = 0; /* Nibble sequential */
945         switch (popts->burst_length) {
946         case DDR_BL8:
947                 bl = 0;
948                 break;
949         case DDR_OTF:
950                 bl = 1;
951                 break;
952         case DDR_BC4:
953                 bl = 2;
954                 break;
955         default:
956                 printf("Error: invalid burst length of %u specified. "
957                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
958                         popts->burst_length);
959                 bl = 1;
960                 break;
961         }
963         sdmode = (0
964                   | ((dll_on & 0x1) << 12)
965                   | ((wr & 0x7) << 9)
966                   | ((dll_rst & 0x1) << 8)
967                   | ((mode & 0x1) << 7)
968                   | (((caslat >> 1) & 0x7) << 4)
969                   | ((bt & 0x1) << 3)
970                   | ((caslat & 1) << 2)
971                   | ((bl & 0x3) << 0)
972                   );
974         ddr->ddr_sdram_mode = (0
975                                | ((esdmode & 0xFFFF) << 16)
976                                | ((sdmode & 0xFFFF) << 0)
977                                );
979         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
981         if (unq_mrs_en) {       /* unique mode registers are supported */
982                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
983                         if (popts->rtt_override)
984                                 rtt = popts->rtt_override_value;
985                         else
986                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
988                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
989                         esdmode |= (0
990                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
991                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
992                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
993                                 );
994                         switch (i) {
995                         case 1:
996                                 ddr->ddr_sdram_mode_3 = (0
997                                        | ((esdmode & 0xFFFF) << 16)
998                                        | ((sdmode & 0xFFFF) << 0)
999                                        );
1000                                 break;
1001                         case 2:
1002                                 ddr->ddr_sdram_mode_5 = (0
1003                                        | ((esdmode & 0xFFFF) << 16)
1004                                        | ((sdmode & 0xFFFF) << 0)
1005                                        );
1006                                 break;
1007                         case 3:
1008                                 ddr->ddr_sdram_mode_7 = (0
1009                                        | ((esdmode & 0xFFFF) << 16)
1010                                        | ((sdmode & 0xFFFF) << 0)
1011                                        );
1012                                 break;
1013                         }
1014                 }
1015                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1016                         ddr->ddr_sdram_mode_3);
1017                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1018                         ddr->ddr_sdram_mode_5);
1019                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1020                         ddr->ddr_sdram_mode_5);
1021         }
1024 #else /* !CONFIG_FSL_DDR3 */
1026 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1027 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1028                                const memctl_options_t *popts,
1029                                const common_timing_params_t *common_dimm,
1030                                unsigned int cas_latency,
1031                                unsigned int additive_latency,
1032                                const unsigned int unq_mrs_en)
1034         unsigned short esdmode;         /* Extended SDRAM mode */
1035         unsigned short sdmode;          /* SDRAM mode */
1037         /*
1038          * FIXME: This ought to be pre-calculated in a
1039          * technology-specific routine,
1040          * e.g. compute_DDR2_mode_register(), and then the
1041          * sdmode and esdmode passed in as part of common_dimm.
1042          */
1044         /* Extended Mode Register */
1045         unsigned int mrs = 0;           /* Mode Register Set */
1046         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1047         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1048         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1049         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1050                                            0x7=OCD default state */
1051         unsigned int rtt;
1052         unsigned int al;                /* Posted CAS# additive latency (AL) */
1053         unsigned int ods = 0;           /* Output Drive Strength:
1054                                                 0 = Full strength (18ohm)
1055                                                 1 = Reduced strength (4ohm) */
1056         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1057                                                        1=Disable (Test/Debug) */
1059         /* Mode Register (MR) */
1060         unsigned int mr;        /* Mode Register Definition */
1061         unsigned int pd;        /* Power-Down Mode */
1062         unsigned int wr;        /* Write Recovery */
1063         unsigned int dll_res;   /* DLL Reset */
1064         unsigned int mode;      /* Normal=0 or Test=1 */
1065         unsigned int caslat = 0;/* CAS# latency */
1066         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1067         unsigned int bt;
1068         unsigned int bl;        /* BL: Burst Length */
1070 #if defined(CONFIG_FSL_DDR2)
1071         const unsigned int mclk_ps = get_memory_clk_period_ps();
1072 #endif
1073         dqs_en = !popts->DQS_config;
1074         rtt = fsl_ddr_get_rtt();
1076         al = additive_latency;
1078         esdmode = (0
1079                 | ((mrs & 0x3) << 14)
1080                 | ((outputs & 0x1) << 12)
1081                 | ((rdqs_en & 0x1) << 11)
1082                 | ((dqs_en & 0x1) << 10)
1083                 | ((ocd & 0x7) << 7)
1084                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1085                 | ((al & 0x7) << 3)
1086                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1087                 | ((ods & 0x1) << 1)
1088                 | ((dll_en & 0x1) << 0)
1089                 );
1091         mr = 0;          /* FIXME: CHECKME */
1093         /*
1094          * 0 = Fast Exit (Normal)
1095          * 1 = Slow Exit (Low Power)
1096          */
1097         pd = 0;
1099 #if defined(CONFIG_FSL_DDR1)
1100         wr = 0;       /* Historical */
1101 #elif defined(CONFIG_FSL_DDR2)
1102         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1103 #endif
1104         dll_res = 0;
1105         mode = 0;
1107 #if defined(CONFIG_FSL_DDR1)
1108         if (1 <= cas_latency && cas_latency <= 4) {
1109                 unsigned char mode_caslat_table[4] = {
1110                         0x5,    /* 1.5 clocks */
1111                         0x2,    /* 2.0 clocks */
1112                         0x6,    /* 2.5 clocks */
1113                         0x3     /* 3.0 clocks */
1114                 };
1115                 caslat = mode_caslat_table[cas_latency - 1];
1116         } else {
1117                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1118         }
1119 #elif defined(CONFIG_FSL_DDR2)
1120         caslat = cas_latency;
1121 #endif
1122         bt = 0;
1124         switch (popts->burst_length) {
1125         case DDR_BL4:
1126                 bl = 2;
1127                 break;
1128         case DDR_BL8:
1129                 bl = 3;
1130                 break;
1131         default:
1132                 printf("Error: invalid burst length of %u specified. "
1133                         " Defaulting to 4 beats.\n",
1134                         popts->burst_length);
1135                 bl = 2;
1136                 break;
1137         }
1139         sdmode = (0
1140                   | ((mr & 0x3) << 14)
1141                   | ((pd & 0x1) << 12)
1142                   | ((wr & 0x7) << 9)
1143                   | ((dll_res & 0x1) << 8)
1144                   | ((mode & 0x1) << 7)
1145                   | ((caslat & 0x7) << 4)
1146                   | ((bt & 0x1) << 3)
1147                   | ((bl & 0x7) << 0)
1148                   );
1150         ddr->ddr_sdram_mode = (0
1151                                | ((esdmode & 0xFFFF) << 16)
1152                                | ((sdmode & 0xFFFF) << 0)
1153                                );
1154         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1156 #endif
1158 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1159 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1161         unsigned int init_value;        /* Initialization value */
1163         init_value = 0xDEADBEEF;
1164         ddr->ddr_data_init = init_value;
1167 /*
1168  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1169  * The old controller on the 8540/60 doesn't have this register.
1170  * Hope it's OK to set it (to 0) anyway.
1171  */
1172 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1173                                          const memctl_options_t *popts)
1175         unsigned int clk_adjust;        /* Clock adjust */
1177         clk_adjust = popts->clk_adjust;
1178         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1179         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1182 /* DDR Initialization Address (DDR_INIT_ADDR) */
1183 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1185         unsigned int init_addr = 0;     /* Initialization address */
1187         ddr->ddr_init_addr = init_addr;
1190 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1191 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1193         unsigned int uia = 0;   /* Use initialization address */
1194         unsigned int init_ext_addr = 0; /* Initialization address */
1196         ddr->ddr_init_ext_addr = (0
1197                                   | ((uia & 0x1) << 31)
1198                                   | (init_ext_addr & 0xF)
1199                                   );
1202 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1203 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1204                                 const memctl_options_t *popts)
1206         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1207         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1208         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1209         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1210         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1212 #if defined(CONFIG_FSL_DDR3)
1213         if (popts->burst_length == DDR_BL8) {
1214                 /* We set BL/2 for fixed BL8 */
1215                 rrt = 0;        /* BL/2 clocks */
1216                 wwt = 0;        /* BL/2 clocks */
1217         } else {
1218                 /* We need to set BL/2 + 2 to BC4 and OTF */
1219                 rrt = 2;        /* BL/2 + 2 clocks */
1220                 wwt = 2;        /* BL/2 + 2 clocks */
1221         }
1222         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1223 #endif
1224         ddr->timing_cfg_4 = (0
1225                              | ((rwt & 0xf) << 28)
1226                              | ((wrt & 0xf) << 24)
1227                              | ((rrt & 0xf) << 20)
1228                              | ((wwt & 0xf) << 16)
1229                              | (dll_lock & 0x3)
1230                              );
1231         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1234 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1235 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1237         unsigned int rodt_on = 0;       /* Read to ODT on */
1238         unsigned int rodt_off = 0;      /* Read to ODT off */
1239         unsigned int wodt_on = 0;       /* Write to ODT on */
1240         unsigned int wodt_off = 0;      /* Write to ODT off */
1242 #if defined(CONFIG_FSL_DDR3)
1243         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1244         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1245         rodt_off = 4;   /*  4 clocks */
1246         wodt_on = 1;    /*  1 clocks */
1247         wodt_off = 4;   /*  4 clocks */
1248 #endif
1250         ddr->timing_cfg_5 = (0
1251                              | ((rodt_on & 0x1f) << 24)
1252                              | ((rodt_off & 0x7) << 20)
1253                              | ((wodt_on & 0x1f) << 12)
1254                              | ((wodt_off & 0x7) << 8)
1255                              );
1256         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1259 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1260 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1262         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1263         /* Normal Operation Full Calibration Time (tZQoper) */
1264         unsigned int zqoper = 0;
1265         /* Normal Operation Short Calibration Time (tZQCS) */
1266         unsigned int zqcs = 0;
1268         if (zq_en) {
1269                 zqinit = 9;     /* 512 clocks */
1270                 zqoper = 8;     /* 256 clocks */
1271                 zqcs = 6;       /* 64 clocks */
1272         }
1274         ddr->ddr_zq_cntl = (0
1275                             | ((zq_en & 0x1) << 31)
1276                             | ((zqinit & 0xF) << 24)
1277                             | ((zqoper & 0xF) << 16)
1278                             | ((zqcs & 0xF) << 8)
1279                             );
1280         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1283 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1284 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1285                                 const memctl_options_t *popts)
1287         /*
1288          * First DQS pulse rising edge after margining mode
1289          * is programmed (tWL_MRD)
1290          */
1291         unsigned int wrlvl_mrd = 0;
1292         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1293         unsigned int wrlvl_odten = 0;
1294         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1295         unsigned int wrlvl_dqsen = 0;
1296         /* WRLVL_SMPL: Write leveling sample time */
1297         unsigned int wrlvl_smpl = 0;
1298         /* WRLVL_WLR: Write leveling repeition time */
1299         unsigned int wrlvl_wlr = 0;
1300         /* WRLVL_START: Write leveling start time */
1301         unsigned int wrlvl_start = 0;
1303         /* suggest enable write leveling for DDR3 due to fly-by topology */
1304         if (wrlvl_en) {
1305                 /* tWL_MRD min = 40 nCK, we set it 64 */
1306                 wrlvl_mrd = 0x6;
1307                 /* tWL_ODTEN 128 */
1308                 wrlvl_odten = 0x7;
1309                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1310                 wrlvl_dqsen = 0x5;
1311                 /*
1312                  * Write leveling sample time at least need 6 clocks
1313                  * higher than tWLO to allow enough time for progagation
1314                  * delay and sampling the prime data bits.
1315                  */
1316                 wrlvl_smpl = 0xf;
1317                 /*
1318                  * Write leveling repetition time
1319                  * at least tWLO + 6 clocks clocks
1320                  * we set it 64
1321                  */
1322                 wrlvl_wlr = 0x6;
1323                 /*
1324                  * Write leveling start time
1325                  * The value use for the DQS_ADJUST for the first sample
1326                  * when write leveling is enabled. It probably needs to be
1327                  * overriden per platform.
1328                  */
1329                 wrlvl_start = 0x8;
1330                 /*
1331                  * Override the write leveling sample and start time
1332                  * according to specific board
1333                  */
1334                 if (popts->wrlvl_override) {
1335                         wrlvl_smpl = popts->wrlvl_sample;
1336                         wrlvl_start = popts->wrlvl_start;
1337                 }
1338         }
1340         ddr->ddr_wrlvl_cntl = (0
1341                                | ((wrlvl_en & 0x1) << 31)
1342                                | ((wrlvl_mrd & 0x7) << 24)
1343                                | ((wrlvl_odten & 0x7) << 20)
1344                                | ((wrlvl_dqsen & 0x7) << 16)
1345                                | ((wrlvl_smpl & 0xf) << 12)
1346                                | ((wrlvl_wlr & 0x7) << 8)
1347                                | ((wrlvl_start & 0x1F) << 0)
1348                                );
1349         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1352 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1353 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1355         /* Self Refresh Idle Threshold */
1356         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1359 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1361         if (popts->addr_hash) {
1362                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1363                 puts("Address hashing enabled.\n");
1364         }
1367 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1369         ddr->ddr_cdr1 = popts->ddr_cdr1;
1370         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1373 unsigned int
1374 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1376         unsigned int res = 0;
1378         /*
1379          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1380          * not set at the same time.
1381          */
1382         if (ddr->ddr_sdram_cfg & 0x10000000
1383             && ddr->ddr_sdram_cfg & 0x00008000) {
1384                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1385                                 " should not be set at the same time.\n");
1386                 res++;
1387         }
1389         return res;
1392 unsigned int
1393 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1394                                fsl_ddr_cfg_regs_t *ddr,
1395                                const common_timing_params_t *common_dimm,
1396                                const dimm_params_t *dimm_params,
1397                                unsigned int dbw_cap_adj,
1398                                unsigned int size_only)
1400         unsigned int i;
1401         unsigned int cas_latency;
1402         unsigned int additive_latency;
1403         unsigned int sr_it;
1404         unsigned int zq_en;
1405         unsigned int wrlvl_en;
1406         unsigned int ip_rev = 0;
1407         unsigned int unq_mrs_en = 0;
1408         int cs_en = 1;
1410         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1412         if (common_dimm == NULL) {
1413                 printf("Error: subset DIMM params struct null pointer\n");
1414                 return 1;
1415         }
1417         /*
1418          * Process overrides first.
1419          *
1420          * FIXME: somehow add dereated caslat to this
1421          */
1422         cas_latency = (popts->cas_latency_override)
1423                 ? popts->cas_latency_override_value
1424                 : common_dimm->lowest_common_SPD_caslat;
1426         additive_latency = (popts->additive_latency_override)
1427                 ? popts->additive_latency_override_value
1428                 : common_dimm->additive_latency;
1430         sr_it = (popts->auto_self_refresh_en)
1431                 ? popts->sr_it
1432                 : 0;
1433         /* ZQ calibration */
1434         zq_en = (popts->zq_en) ? 1 : 0;
1435         /* write leveling */
1436         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1438         /* Chip Select Memory Bounds (CSn_BNDS) */
1439         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1440                 unsigned long long ea, sa;
1441                 unsigned int cs_per_dimm
1442                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1443                 unsigned int dimm_number
1444                         = i / cs_per_dimm;
1445                 unsigned long long rank_density
1446                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1448                 if (dimm_params[dimm_number].n_ranks == 0) {
1449                         debug("Skipping setup of CS%u "
1450                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1451                         continue;
1452                 }
1453                 if (popts->memctl_interleaving) {
1454                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1455                         case FSL_DDR_CS0_CS1_CS2_CS3:
1456                                 break;
1457                         case FSL_DDR_CS0_CS1:
1458                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1459                                 if (i > 1)
1460                                         cs_en = 0;
1461                                 break;
1462                         case FSL_DDR_CS2_CS3:
1463                         default:
1464                                 if (i > 0)
1465                                         cs_en = 0;
1466                                 break;
1467                         }
1468                         sa = common_dimm->base_address;
1469                         ea = common_dimm->total_mem - 1;
1470                 } else if (!popts->memctl_interleaving) {
1471                         /*
1472                          * If memory interleaving between controllers is NOT
1473                          * enabled, the starting address for each memory
1474                          * controller is distinct.  However, because rank
1475                          * interleaving is enabled, the starting and ending
1476                          * addresses of the total memory on that memory
1477                          * controller needs to be programmed into its
1478                          * respective CS0_BNDS.
1479                          */
1480                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1481                         case FSL_DDR_CS0_CS1_CS2_CS3:
1482                                 sa = common_dimm->base_address;
1483                                 ea = common_dimm->total_mem - 1;
1484                                 break;
1485                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1486                                 if ((i >= 2) && (dimm_number == 0)) {
1487                                         sa = dimm_params[dimm_number].base_address +
1488                                               2 * rank_density;
1489                                         ea = sa + 2 * rank_density - 1;
1490                                 } else {
1491                                         sa = dimm_params[dimm_number].base_address;
1492                                         ea = sa + 2 * rank_density - 1;
1493                                 }
1494                                 break;
1495                         case FSL_DDR_CS0_CS1:
1496                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1497                                         sa = dimm_params[dimm_number].base_address;
1498                                         ea = sa + rank_density - 1;
1499                                         if (i != 1)
1500                                                 sa += (i % cs_per_dimm) * rank_density;
1501                                         ea += (i % cs_per_dimm) * rank_density;
1502                                 } else {
1503                                         sa = 0;
1504                                         ea = 0;
1505                                 }
1506                                 if (i == 0)
1507                                         ea += rank_density;
1508                                 break;
1509                         case FSL_DDR_CS2_CS3:
1510                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1511                                         sa = dimm_params[dimm_number].base_address;
1512                                         ea = sa + rank_density - 1;
1513                                         if (i != 3)
1514                                                 sa += (i % cs_per_dimm) * rank_density;
1515                                         ea += (i % cs_per_dimm) * rank_density;
1516                                 } else {
1517                                         sa = 0;
1518                                         ea = 0;
1519                                 }
1520                                 if (i == 2)
1521                                         ea += (rank_density >> dbw_cap_adj);
1522                                 break;
1523                         default:  /* No bank(chip-select) interleaving */
1524                                 sa = dimm_params[dimm_number].base_address;
1525                                 ea = sa + rank_density - 1;
1526                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1527                                         sa += (i % cs_per_dimm) * rank_density;
1528                                         ea += (i % cs_per_dimm) * rank_density;
1529                                 } else {
1530                                         sa = 0;
1531                                         ea = 0;
1532                                 }
1533                                 break;
1534                         }
1535                 }
1537                 sa >>= 24;
1538                 ea >>= 24;
1540                 ddr->cs[i].bnds = (0
1541                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1542                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1543                         );
1545                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1546                 if (cs_en) {
1547                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1548                         set_csn_config_2(i, ddr);
1549                 } else
1550                         debug("CS%d is disabled.\n", i);
1551         }
1553         /*
1554          * In the case we only need to compute the ddr sdram size, we only need
1555          * to set csn registers, so return from here.
1556          */
1557         if (size_only)
1558                 return 0;
1560         set_ddr_eor(ddr, popts);
1562 #if !defined(CONFIG_FSL_DDR1)
1563         set_timing_cfg_0(ddr, popts);
1564 #endif
1566         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
1567         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1568         set_timing_cfg_2(ddr, popts, common_dimm,
1569                                 cas_latency, additive_latency);
1571         set_ddr_cdr1(ddr, popts);
1572         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1573         ip_rev = fsl_ddr_get_version();
1574         if (ip_rev > 0x40400)
1575                 unq_mrs_en = 1;
1577         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1578         set_ddr_sdram_mode(ddr, popts, common_dimm,
1579                                 cas_latency, additive_latency, unq_mrs_en);
1580         set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1581         set_ddr_sdram_interval(ddr, popts, common_dimm);
1582         set_ddr_data_init(ddr);
1583         set_ddr_sdram_clk_cntl(ddr, popts);
1584         set_ddr_init_addr(ddr);
1585         set_ddr_init_ext_addr(ddr);
1586         set_timing_cfg_4(ddr, popts);
1587         set_timing_cfg_5(ddr, cas_latency);
1589         set_ddr_zq_cntl(ddr, zq_en);
1590         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1592         set_ddr_sr_cntr(ddr, sr_it);
1594         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1596         return check_fsl_memctl_config_regs(ddr);