omap5_common.h: Switch to ext4
[glsdk/glsdk-u-boot.git] / arch / powerpc / cpu / ppc4xx / 44x_spd_ddr2.c
1 /*
2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4  * DDR2 controller (non Denali Core). Those currently are:
5  *
6  * 405:         405EX(r)
7  * 440/460:     440SP/440SPe/460EX/460GT
8  *
9  * Copyright (c) 2008 Nuovation System Designs, LLC
10  *   Grant Erickson <gerickson@nuovations.com>
12  * (C) Copyright 2007-2009
13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
14  *
15  * COPYRIGHT   AMCC   CORPORATION 2004
16  *
17  * See file CREDITS for list of people who contributed to this
18  * project.
19  *
20  * This program is free software; you can redistribute it and/or
21  * modify it under the terms of the GNU General Public License as
22  * published by the Free Software Foundation; either version 2 of
23  * the License, or (at your option) any later version.
24  *
25  * This program is distributed in the hope that it will be useful,
26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
28  * GNU General Public License for more details.
29  *
30  * You should have received a copy of the GNU General Public License
31  * along with this program; if not, write to the Free Software
32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33  * MA 02111-1307 USA
34  *
35  */
37 /* define DEBUG for debugging output (obviously ;-)) */
38 #if 0
39 #define DEBUG
40 #endif
42 #include <common.h>
43 #include <command.h>
44 #include <asm/ppc4xx.h>
45 #include <i2c.h>
46 #include <asm/io.h>
47 #include <asm/processor.h>
48 #include <asm/mmu.h>
49 #include <asm/cache.h>
51 #include "ecc.h"
53 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
54         do {                                                            \
55                 u32 data;                                               \
56                 mfsdram(SDRAM_##mnemonic, data);                        \
57                 printf("%20s[%02x] = 0x%08X\n",                         \
58                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
59         } while (0)
61 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
62         do {                                                            \
63                 u32 data;                                               \
64                 data = mfdcr(SDRAM_##mnemonic);                         \
65                 printf("%20s[%02x] = 0x%08X\n",                         \
66                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
67         } while (0)
69 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
70 static void update_rdcc(void)
71 {
72         u32 val;
74         /*
75          * Complete RDSS configuration as mentioned on page 7 of the AMCC
76          * PowerPC440SP/SPe DDR2 application note:
77          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
78          *
79          * Or item #10 "10. Complete RDSS configuration" in chapter
80          * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
81          * manual.
82          */
83         mfsdram(SDRAM_RTSR, val);
84         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
85                 mfsdram(SDRAM_RDCC, val);
86                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
87                         val += 0x40000000;
88                         mtsdram(SDRAM_RDCC, val);
89                 }
90         }
91 }
92 #endif
94 #if defined(CONFIG_440)
95 /*
96  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
97  * memory region. Right now the cache should still be disabled in U-Boot
98  * because of the EMAC driver, that need its buffer descriptor to be located
99  * in non cached memory.
100  *
101  * If at some time this restriction doesn't apply anymore, just define
102  * CONFIG_4xx_DCACHE in the board config file and this code should setup
103  * everything correctly.
104  */
105 #ifdef CONFIG_4xx_DCACHE
106 /* enable caching on SDRAM */
107 #define MY_TLB_WORD2_I_ENABLE           0
108 #else
109 /* disable caching on SDRAM */
110 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
111 #endif /* CONFIG_4xx_DCACHE */
113 void dcbz_area(u32 start_address, u32 num_bytes);
114 #endif /* CONFIG_440 */
116 #define MAXRANKS        4
117 #define MAXBXCF         4
119 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
121 #if !defined(CONFIG_NAND_SPL)
122 /*-----------------------------------------------------------------------------+
123  * sdram_memsize
124  *-----------------------------------------------------------------------------*/
125 phys_size_t sdram_memsize(void)
127         phys_size_t mem_size;
128         unsigned long mcopt2;
129         unsigned long mcstat;
130         unsigned long mb0cf;
131         unsigned long sdsz;
132         unsigned long i;
134         mem_size = 0;
136         mfsdram(SDRAM_MCOPT2, mcopt2);
137         mfsdram(SDRAM_MCSTAT, mcstat);
139         /* DDR controller must be enabled and not in self-refresh. */
140         /* Otherwise memsize is zero. */
141         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
142             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
143             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
144                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
145                 for (i = 0; i < MAXBXCF; i++) {
146                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
147                         /* Banks enabled */
148                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
149 #if defined(CONFIG_440)
150                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
151 #else
152                                 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
153 #endif
154                                 switch(sdsz) {
155                                 case SDRAM_RXBAS_SDSZ_8:
156                                         mem_size+=8;
157                                         break;
158                                 case SDRAM_RXBAS_SDSZ_16:
159                                         mem_size+=16;
160                                         break;
161                                 case SDRAM_RXBAS_SDSZ_32:
162                                         mem_size+=32;
163                                         break;
164                                 case SDRAM_RXBAS_SDSZ_64:
165                                         mem_size+=64;
166                                         break;
167                                 case SDRAM_RXBAS_SDSZ_128:
168                                         mem_size+=128;
169                                         break;
170                                 case SDRAM_RXBAS_SDSZ_256:
171                                         mem_size+=256;
172                                         break;
173                                 case SDRAM_RXBAS_SDSZ_512:
174                                         mem_size+=512;
175                                         break;
176                                 case SDRAM_RXBAS_SDSZ_1024:
177                                         mem_size+=1024;
178                                         break;
179                                 case SDRAM_RXBAS_SDSZ_2048:
180                                         mem_size+=2048;
181                                         break;
182                                 case SDRAM_RXBAS_SDSZ_4096:
183                                         mem_size+=4096;
184                                         break;
185                                 default:
186                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
187                                                , sdsz);
188                                         mem_size=0;
189                                         break;
190                                 }
191                         }
192                 }
193         }
195         return mem_size << 20;
198 /*-----------------------------------------------------------------------------+
199  * is_ecc_enabled
200  *-----------------------------------------------------------------------------*/
201 static unsigned long is_ecc_enabled(void)
203         unsigned long val;
205         mfsdram(SDRAM_MCOPT1, val);
207         return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
210 /*-----------------------------------------------------------------------------+
211  * board_add_ram_info
212  *-----------------------------------------------------------------------------*/
213 void board_add_ram_info(int use_default)
215         PPC4xx_SYS_INFO board_cfg;
216         u32 val;
218         if (is_ecc_enabled())
219                 puts(" (ECC");
220         else
221                 puts(" (ECC not");
223         get_sys_info(&board_cfg);
225 #if defined(CONFIG_405EX)
226         val = board_cfg.freqPLB;
227 #else
228         mfsdr(SDR0_DDR0, val);
229         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
230 #endif
231         printf(" enabled, %d MHz", (val * 2) / 1000000);
233         mfsdram(SDRAM_MMODE, val);
234         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
235         printf(", CL%d)", val);
237 #endif /* !CONFIG_NAND_SPL */
239 #if defined(CONFIG_SPD_EEPROM)
241 /*-----------------------------------------------------------------------------+
242  * Defines
243  *-----------------------------------------------------------------------------*/
244 #ifndef TRUE
245 #define TRUE            1
246 #endif
247 #ifndef FALSE
248 #define FALSE           0
249 #endif
251 #define SDRAM_DDR1      1
252 #define SDRAM_DDR2      2
253 #define SDRAM_NONE      0
255 #define MAXDIMMS        2
256 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
258 #define ONE_BILLION     1000000000
260 #define CMD_NOP         (7 << 19)
261 #define CMD_PRECHARGE   (2 << 19)
262 #define CMD_REFRESH     (1 << 19)
263 #define CMD_EMR         (0 << 19)
264 #define CMD_READ        (5 << 19)
265 #define CMD_WRITE       (4 << 19)
267 #define SELECT_MR       (0 << 16)
268 #define SELECT_EMR      (1 << 16)
269 #define SELECT_EMR2     (2 << 16)
270 #define SELECT_EMR3     (3 << 16)
272 /* MR */
273 #define DLL_RESET       0x00000100
275 #define WRITE_RECOV_2   (1 << 9)
276 #define WRITE_RECOV_3   (2 << 9)
277 #define WRITE_RECOV_4   (3 << 9)
278 #define WRITE_RECOV_5   (4 << 9)
279 #define WRITE_RECOV_6   (5 << 9)
281 #define BURST_LEN_4     0x00000002
283 /* EMR */
284 #define ODT_0_OHM       0x00000000
285 #define ODT_50_OHM      0x00000044
286 #define ODT_75_OHM      0x00000004
287 #define ODT_150_OHM     0x00000040
289 #define ODS_FULL        0x00000000
290 #define ODS_REDUCED     0x00000002
291 #define OCD_CALIB_DEF   0x00000380
293 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
294 #define ODT_EB0R        (0x80000000 >> 8)
295 #define ODT_EB0W        (0x80000000 >> 7)
296 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
297 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
298 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
300 /* Defines for the Read Cycle Delay test */
301 #define NUMMEMTESTS     8
302 #define NUMMEMWORDS     8
303 #define NUMLOOPS        64              /* memory test loops */
305 /*
306  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
307  * To support such configurations, we "only" map the first 2GB via the TLB's. We
308  * need some free virtual address space for the remaining peripherals like, SoC
309  * devices, FLASH etc.
310  *
311  * Note that ECC is currently not supported on configurations with more than 2GB
312  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
313  * the ECC parity byte of the remaining area can't be written.
314  */
316 /*
317  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
318  */
319 void __spd_ddr_init_hang (void)
321         hang ();
323 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
325 /*
326  * To provide an interface for board specific config values in this common
327  * DDR setup code, we implement he "weak" default functions here. They return
328  * the default value back to the caller.
329  *
330  * Please see include/configs/yucca.h for an example fora board specific
331  * implementation.
332  */
333 u32 __ddr_wrdtr(u32 default_val)
335         return default_val;
337 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
339 u32 __ddr_clktr(u32 default_val)
341         return default_val;
343 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
346 /* Private Structure Definitions */
348 /* enum only to ease code for cas latency setting */
349 typedef enum ddr_cas_id {
350         DDR_CAS_2      = 20,
351         DDR_CAS_2_5    = 25,
352         DDR_CAS_3      = 30,
353         DDR_CAS_4      = 40,
354         DDR_CAS_5      = 50
355 } ddr_cas_id_t;
357 /*-----------------------------------------------------------------------------+
358  * Prototypes
359  *-----------------------------------------------------------------------------*/
360 static void get_spd_info(unsigned long *dimm_populated,
361                          unsigned char *iic0_dimm_addr,
362                          unsigned long num_dimm_banks);
363 static void check_mem_type(unsigned long *dimm_populated,
364                            unsigned char *iic0_dimm_addr,
365                            unsigned long num_dimm_banks);
366 static void check_frequency(unsigned long *dimm_populated,
367                             unsigned char *iic0_dimm_addr,
368                             unsigned long num_dimm_banks);
369 static void check_rank_number(unsigned long *dimm_populated,
370                               unsigned char *iic0_dimm_addr,
371                               unsigned long num_dimm_banks);
372 static void check_voltage_type(unsigned long *dimm_populated,
373                                unsigned char *iic0_dimm_addr,
374                                unsigned long num_dimm_banks);
375 static void program_memory_queue(unsigned long *dimm_populated,
376                                  unsigned char *iic0_dimm_addr,
377                                  unsigned long num_dimm_banks);
378 static void program_codt(unsigned long *dimm_populated,
379                          unsigned char *iic0_dimm_addr,
380                          unsigned long num_dimm_banks);
381 static void program_mode(unsigned long *dimm_populated,
382                          unsigned char *iic0_dimm_addr,
383                          unsigned long num_dimm_banks,
384                          ddr_cas_id_t *selected_cas,
385                          int *write_recovery);
386 static void program_tr(unsigned long *dimm_populated,
387                        unsigned char *iic0_dimm_addr,
388                        unsigned long num_dimm_banks);
389 static void program_rtr(unsigned long *dimm_populated,
390                         unsigned char *iic0_dimm_addr,
391                         unsigned long num_dimm_banks);
392 static void program_bxcf(unsigned long *dimm_populated,
393                          unsigned char *iic0_dimm_addr,
394                          unsigned long num_dimm_banks);
395 static void program_copt1(unsigned long *dimm_populated,
396                           unsigned char *iic0_dimm_addr,
397                           unsigned long num_dimm_banks);
398 static void program_initplr(unsigned long *dimm_populated,
399                             unsigned char *iic0_dimm_addr,
400                             unsigned long num_dimm_banks,
401                             ddr_cas_id_t selected_cas,
402                             int write_recovery);
403 #ifdef CONFIG_DDR_ECC
404 static void program_ecc(unsigned long *dimm_populated,
405                         unsigned char *iic0_dimm_addr,
406                         unsigned long num_dimm_banks,
407                         unsigned long tlb_word2_i_value);
408 #endif
409 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
410 static void program_DQS_calibration(unsigned long *dimm_populated,
411                                 unsigned char *iic0_dimm_addr,
412                                 unsigned long num_dimm_banks);
413 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
414 static void     test(void);
415 #else
416 static void     DQS_calibration_process(void);
417 #endif
418 #endif
420 static unsigned char spd_read(uchar chip, uint addr)
422         unsigned char data[2];
424         if (i2c_probe(chip) == 0)
425                 if (i2c_read(chip, addr, 1, data, 1) == 0)
426                         return data[0];
428         return 0;
431 /*-----------------------------------------------------------------------------+
432  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
433  * Note: This routine runs from flash with a stack set up in the chip's
434  * sram space.  It is important that the routine does not require .sbss, .bss or
435  * .data sections.  It also cannot call routines that require these sections.
436  *-----------------------------------------------------------------------------*/
437 /*-----------------------------------------------------------------------------
438  * Function:     initdram
439  * Description:  Configures SDRAM memory banks for DDR operation.
440  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
441  *               via the IIC bus and then configures the DDR SDRAM memory
442  *               banks appropriately. If Auto Memory Configuration is
443  *               not used, it is assumed that no DIMM is plugged
444  *-----------------------------------------------------------------------------*/
445 phys_size_t initdram(int board_type)
447         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
448         unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
449         unsigned long num_dimm_banks;           /* on board dimm banks */
450         unsigned long val;
451         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
452         int write_recovery;
453         phys_size_t dram_size = 0;
455         num_dimm_banks = sizeof(iic0_dimm_addr);
457         /*------------------------------------------------------------------
458          * Reset the DDR-SDRAM controller.
459          *-----------------------------------------------------------------*/
460         mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
461         mtsdr(SDR0_SRST, 0x00000000);
463         /*
464          * Make sure I2C controller is initialized
465          * before continuing.
466          */
468         /* switch to correct I2C bus */
469         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
470         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
472         /*------------------------------------------------------------------
473          * Clear out the serial presence detect buffers.
474          * Perform IIC reads from the dimm.  Fill in the spds.
475          * Check to see if the dimm slots are populated
476          *-----------------------------------------------------------------*/
477         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
479         /*------------------------------------------------------------------
480          * Check the memory type for the dimms plugged.
481          *-----------------------------------------------------------------*/
482         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
484         /*------------------------------------------------------------------
485          * Check the frequency supported for the dimms plugged.
486          *-----------------------------------------------------------------*/
487         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
489         /*------------------------------------------------------------------
490          * Check the total rank number.
491          *-----------------------------------------------------------------*/
492         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
494         /*------------------------------------------------------------------
495          * Check the voltage type for the dimms plugged.
496          *-----------------------------------------------------------------*/
497         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
499         /*------------------------------------------------------------------
500          * Program SDRAM controller options 2 register
501          * Except Enabling of the memory controller.
502          *-----------------------------------------------------------------*/
503         mfsdram(SDRAM_MCOPT2, val);
504         mtsdram(SDRAM_MCOPT2,
505                 (val &
506                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
507                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
508                    SDRAM_MCOPT2_ISIE_MASK))
509                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
510                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
511                    SDRAM_MCOPT2_ISIE_ENABLE));
513         /*------------------------------------------------------------------
514          * Program SDRAM controller options 1 register
515          * Note: Does not enable the memory controller.
516          *-----------------------------------------------------------------*/
517         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
519         /*------------------------------------------------------------------
520          * Set the SDRAM Controller On Die Termination Register
521          *-----------------------------------------------------------------*/
522         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
524         /*------------------------------------------------------------------
525          * Program SDRAM refresh register.
526          *-----------------------------------------------------------------*/
527         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
529         /*------------------------------------------------------------------
530          * Program SDRAM mode register.
531          *-----------------------------------------------------------------*/
532         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
533                      &selected_cas, &write_recovery);
535         /*------------------------------------------------------------------
536          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
537          *-----------------------------------------------------------------*/
538         mfsdram(SDRAM_WRDTR, val);
539         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
540                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
542         /*------------------------------------------------------------------
543          * Set the SDRAM Clock Timing Register
544          *-----------------------------------------------------------------*/
545         mfsdram(SDRAM_CLKTR, val);
546         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
547                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
549         /*------------------------------------------------------------------
550          * Program the BxCF registers.
551          *-----------------------------------------------------------------*/
552         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
554         /*------------------------------------------------------------------
555          * Program SDRAM timing registers.
556          *-----------------------------------------------------------------*/
557         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
559         /*------------------------------------------------------------------
560          * Set the Extended Mode register
561          *-----------------------------------------------------------------*/
562         mfsdram(SDRAM_MEMODE, val);
563         mtsdram(SDRAM_MEMODE,
564                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
565                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
566                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
567                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
569         /*------------------------------------------------------------------
570          * Program Initialization preload registers.
571          *-----------------------------------------------------------------*/
572         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
573                         selected_cas, write_recovery);
575         /*------------------------------------------------------------------
576          * Delay to ensure 200usec have elapsed since reset.
577          *-----------------------------------------------------------------*/
578         udelay(400);
580         /*------------------------------------------------------------------
581          * Set the memory queue core base addr.
582          *-----------------------------------------------------------------*/
583         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
585         /*------------------------------------------------------------------
586          * Program SDRAM controller options 2 register
587          * Enable the memory controller.
588          *-----------------------------------------------------------------*/
589         mfsdram(SDRAM_MCOPT2, val);
590         mtsdram(SDRAM_MCOPT2,
591                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
592                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
593                          SDRAM_MCOPT2_IPTR_EXECUTE);
595         /*------------------------------------------------------------------
596          * Wait for IPTR_EXECUTE init sequence to complete.
597          *-----------------------------------------------------------------*/
598         do {
599                 mfsdram(SDRAM_MCSTAT, val);
600         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
602         /* enable the controller only after init sequence completes */
603         mfsdram(SDRAM_MCOPT2, val);
604         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
606         /* Make sure delay-line calibration is done before proceeding */
607         do {
608                 mfsdram(SDRAM_DLCR, val);
609         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
611         /* get installed memory size */
612         dram_size = sdram_memsize();
614         /*
615          * Limit size to 2GB
616          */
617         if (dram_size > CONFIG_MAX_MEM_MAPPED)
618                 dram_size = CONFIG_MAX_MEM_MAPPED;
620         /* and program tlb entries for this size (dynamic) */
622         /*
623          * Program TLB entries with caches enabled, for best performace
624          * while auto-calibrating and ECC generation
625          */
626         program_tlb(0, 0, dram_size, 0);
628         /*------------------------------------------------------------------
629          * DQS calibration.
630          *-----------------------------------------------------------------*/
631 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
632         DQS_autocalibration();
633 #else
634         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
635 #endif
636         /*
637          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
638          * PowerPC440SP/SPe DDR2 application note:
639          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
640          */
641         update_rdcc();
643 #ifdef CONFIG_DDR_ECC
644         /*------------------------------------------------------------------
645          * If ecc is enabled, initialize the parity bits.
646          *-----------------------------------------------------------------*/
647         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
648 #endif
650         /*
651          * Flush the dcache before removing the TLB with caches
652          * enabled. Otherwise this might lead to problems later on,
653          * e.g. while booting Linux (as seen on ICON-440SPe).
654          */
655         flush_dcache();
657         /*
658          * Now after initialization (auto-calibration and ECC generation)
659          * remove the TLB entries with caches enabled and program again with
660          * desired cache functionality
661          */
662         remove_tlb(0, dram_size);
663         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
665         ppc4xx_ibm_ddr2_register_dump();
667         /*
668          * Clear potential errors resulting from auto-calibration.
669          * If not done, then we could get an interrupt later on when
670          * exceptions are enabled.
671          */
672         set_mcsr(get_mcsr());
674         return sdram_memsize();
677 static void get_spd_info(unsigned long *dimm_populated,
678                          unsigned char *iic0_dimm_addr,
679                          unsigned long num_dimm_banks)
681         unsigned long dimm_num;
682         unsigned long dimm_found;
683         unsigned char num_of_bytes;
684         unsigned char total_size;
686         dimm_found = FALSE;
687         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
688                 num_of_bytes = 0;
689                 total_size = 0;
691                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
692                 debug("\nspd_read(0x%x) returned %d\n",
693                       iic0_dimm_addr[dimm_num], num_of_bytes);
694                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
695                 debug("spd_read(0x%x) returned %d\n",
696                       iic0_dimm_addr[dimm_num], total_size);
698                 if ((num_of_bytes != 0) && (total_size != 0)) {
699                         dimm_populated[dimm_num] = TRUE;
700                         dimm_found = TRUE;
701                         debug("DIMM slot %lu: populated\n", dimm_num);
702                 } else {
703                         dimm_populated[dimm_num] = FALSE;
704                         debug("DIMM slot %lu: Not populated\n", dimm_num);
705                 }
706         }
708         if (dimm_found == FALSE) {
709                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
710                 spd_ddr_init_hang ();
711         }
715 /*------------------------------------------------------------------
716  * For the memory DIMMs installed, this routine verifies that they
717  * really are DDR specific DIMMs.
718  *-----------------------------------------------------------------*/
719 static void check_mem_type(unsigned long *dimm_populated,
720                            unsigned char *iic0_dimm_addr,
721                            unsigned long num_dimm_banks)
723         unsigned long dimm_num;
724         unsigned long dimm_type;
726         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
727                 if (dimm_populated[dimm_num] == TRUE) {
728                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
729                         switch (dimm_type) {
730                         case 1:
731                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
732                                        "slot %d.\n", (unsigned int)dimm_num);
733                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
734                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
735                                 spd_ddr_init_hang ();
736                                 break;
737                         case 2:
738                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
739                                        (unsigned int)dimm_num);
740                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
741                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
742                                 spd_ddr_init_hang ();
743                                 break;
744                         case 3:
745                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
746                                        (unsigned int)dimm_num);
747                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
748                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
749                                 spd_ddr_init_hang ();
750                                 break;
751                         case 4:
752                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
753                                        (unsigned int)dimm_num);
754                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
755                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
756                                 spd_ddr_init_hang ();
757                                 break;
758                         case 5:
759                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
760                                        (unsigned int)dimm_num);
761                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
762                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
763                                 spd_ddr_init_hang ();
764                                 break;
765                         case 6:
766                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
767                                        (unsigned int)dimm_num);
768                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
769                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
770                                 spd_ddr_init_hang ();
771                                 break;
772                         case 7:
773                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
774                                 dimm_populated[dimm_num] = SDRAM_DDR1;
775                                 break;
776                         case 8:
777                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
778                                 dimm_populated[dimm_num] = SDRAM_DDR2;
779                                 break;
780                         default:
781                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
782                                        (unsigned int)dimm_num);
783                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
784                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
785                                 spd_ddr_init_hang ();
786                                 break;
787                         }
788                 }
789         }
790         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
791                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
792                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
793                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
794                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
795                         spd_ddr_init_hang ();
796                 }
797         }
800 /*------------------------------------------------------------------
801  * For the memory DIMMs installed, this routine verifies that
802  * frequency previously calculated is supported.
803  *-----------------------------------------------------------------*/
804 static void check_frequency(unsigned long *dimm_populated,
805                             unsigned char *iic0_dimm_addr,
806                             unsigned long num_dimm_banks)
808         unsigned long dimm_num;
809         unsigned long tcyc_reg;
810         unsigned long cycle_time;
811         unsigned long calc_cycle_time;
812         unsigned long sdram_freq;
813         unsigned long sdr_ddrpll;
814         PPC4xx_SYS_INFO board_cfg;
816         /*------------------------------------------------------------------
817          * Get the board configuration info.
818          *-----------------------------------------------------------------*/
819         get_sys_info(&board_cfg);
821         mfsdr(SDR0_DDR0, sdr_ddrpll);
822         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
824         /*
825          * calc_cycle_time is calculated from DDR frequency set by board/chip
826          * and is expressed in multiple of 10 picoseconds
827          * to match the way DIMM cycle time is calculated below.
828          */
829         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
831         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
832                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
833                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
834                         /*
835                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
836                          * the higher order nibble (bits 4-7) designates the cycle time
837                          * to a granularity of 1ns;
838                          * the value presented by the lower order nibble (bits 0-3)
839                          * has a granularity of .1ns and is added to the value designated
840                          * by the higher nibble. In addition, four lines of the lower order
841                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
842                          */
843                          /* Convert from hex to decimal */
844                         if ((tcyc_reg & 0x0F) == 0x0D)
845                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
846                         else if ((tcyc_reg & 0x0F) == 0x0C)
847                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
848                         else if ((tcyc_reg & 0x0F) == 0x0B)
849                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
850                         else if ((tcyc_reg & 0x0F) == 0x0A)
851                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
852                         else
853                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
854                                         ((tcyc_reg & 0x0F)*10);
855                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
857                         if  (cycle_time > (calc_cycle_time + 10)) {
858                                 /*
859                                  * the provided sdram cycle_time is too small
860                                  * for the available DIMM cycle_time.
861                                  * The additionnal 100ps is here to accept a small incertainty.
862                                  */
863                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
864                                        "slot %d \n while calculated cycle time is %d ps.\n",
865                                        (unsigned int)(cycle_time*10),
866                                        (unsigned int)dimm_num,
867                                        (unsigned int)(calc_cycle_time*10));
868                                 printf("Replace the DIMM, or change DDR frequency via "
869                                        "strapping bits.\n\n");
870                                 spd_ddr_init_hang ();
871                         }
872                 }
873         }
876 /*------------------------------------------------------------------
877  * For the memory DIMMs installed, this routine verifies two
878  * ranks/banks maximum are availables.
879  *-----------------------------------------------------------------*/
880 static void check_rank_number(unsigned long *dimm_populated,
881                               unsigned char *iic0_dimm_addr,
882                               unsigned long num_dimm_banks)
884         unsigned long dimm_num;
885         unsigned long dimm_rank;
886         unsigned long total_rank = 0;
888         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
889                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
890                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
891                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
892                                 dimm_rank = (dimm_rank & 0x0F) +1;
893                         else
894                                 dimm_rank = dimm_rank & 0x0F;
897                         if (dimm_rank > MAXRANKS) {
898                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
899                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
900                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
901                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
902                                 spd_ddr_init_hang ();
903                         } else
904                                 total_rank += dimm_rank;
905                 }
906                 if (total_rank > MAXRANKS) {
907                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
908                                "for all slots.\n", (unsigned int)total_rank);
909                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
910                         printf("Remove one of the DIMM modules.\n\n");
911                         spd_ddr_init_hang ();
912                 }
913         }
916 /*------------------------------------------------------------------
917  * only support 2.5V modules.
918  * This routine verifies this.
919  *-----------------------------------------------------------------*/
920 static void check_voltage_type(unsigned long *dimm_populated,
921                                unsigned char *iic0_dimm_addr,
922                                unsigned long num_dimm_banks)
924         unsigned long dimm_num;
925         unsigned long voltage_type;
927         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
928                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
929                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
930                         switch (voltage_type) {
931                         case 0x00:
932                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
933                                 printf("This DIMM is 5.0 Volt/TTL.\n");
934                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
935                                        (unsigned int)dimm_num);
936                                 spd_ddr_init_hang ();
937                                 break;
938                         case 0x01:
939                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
940                                 printf("This DIMM is LVTTL.\n");
941                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
942                                        (unsigned int)dimm_num);
943                                 spd_ddr_init_hang ();
944                                 break;
945                         case 0x02:
946                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
947                                 printf("This DIMM is 1.5 Volt.\n");
948                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
949                                        (unsigned int)dimm_num);
950                                 spd_ddr_init_hang ();
951                                 break;
952                         case 0x03:
953                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
954                                 printf("This DIMM is 3.3 Volt/TTL.\n");
955                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
956                                        (unsigned int)dimm_num);
957                                 spd_ddr_init_hang ();
958                                 break;
959                         case 0x04:
960                                 /* 2.5 Voltage only for DDR1 */
961                                 break;
962                         case 0x05:
963                                 /* 1.8 Voltage only for DDR2 */
964                                 break;
965                         default:
966                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
967                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
968                                        (unsigned int)dimm_num);
969                                 spd_ddr_init_hang ();
970                                 break;
971                         }
972                 }
973         }
976 /*-----------------------------------------------------------------------------+
977  * program_copt1.
978  *-----------------------------------------------------------------------------*/
979 static void program_copt1(unsigned long *dimm_populated,
980                           unsigned char *iic0_dimm_addr,
981                           unsigned long num_dimm_banks)
983         unsigned long dimm_num;
984         unsigned long mcopt1;
985         unsigned long ecc_enabled;
986         unsigned long ecc = 0;
987         unsigned long data_width = 0;
988         unsigned long dimm_32bit;
989         unsigned long dimm_64bit;
990         unsigned long registered = 0;
991         unsigned long attribute = 0;
992         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
993         unsigned long bankcount;
994         unsigned long val;
996 #ifdef CONFIG_DDR_ECC
997         ecc_enabled = TRUE;
998 #else
999         ecc_enabled = FALSE;
1000 #endif
1001         dimm_32bit = FALSE;
1002         dimm_64bit = FALSE;
1003         buf0 = FALSE;
1004         buf1 = FALSE;
1006         /*------------------------------------------------------------------
1007          * Set memory controller options reg 1, SDRAM_MCOPT1.
1008          *-----------------------------------------------------------------*/
1009         mfsdram(SDRAM_MCOPT1, val);
1010         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
1011                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
1012                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
1013                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
1014                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1015                          SDRAM_MCOPT1_DREF_MASK);
1017         mcopt1 |= SDRAM_MCOPT1_QDEP;
1018         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1019         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1020         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1021         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1022         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1024         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1025                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1026                         /* test ecc support */
1027                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1028                         if (ecc != 0x02) /* ecc not supported */
1029                                 ecc_enabled = FALSE;
1031                         /* test bank count */
1032                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1033                         if (bankcount == 0x04) /* bank count = 4 */
1034                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1035                         else /* bank count = 8 */
1036                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1038                         /* test for buffered/unbuffered, registered, differential clocks */
1039                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1040                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1042                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1043                         if (dimm_num == 0) {
1044                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1045                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1046                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1047                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1048                                 if (registered == 1) { /* DDR2 always buffered */
1049                                         /* TODO: what about above  comments ? */
1050                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1051                                         buf0 = TRUE;
1052                                 } else {
1053                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1054                                         if ((attribute & 0x02) == 0x00) {
1055                                                 /* buffered not supported */
1056                                                 buf0 = FALSE;
1057                                         } else {
1058                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1059                                                 buf0 = TRUE;
1060                                         }
1061                                 }
1062                         }
1063                         else if (dimm_num == 1) {
1064                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1065                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1066                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1067                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1068                                 if (registered == 1) {
1069                                         /* DDR2 always buffered */
1070                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1071                                         buf1 = TRUE;
1072                                 } else {
1073                                         if ((attribute & 0x02) == 0x00) {
1074                                                 /* buffered not supported */
1075                                                 buf1 = FALSE;
1076                                         } else {
1077                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1078                                                 buf1 = TRUE;
1079                                         }
1080                                 }
1081                         }
1083                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1084                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1085                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1087                         switch (data_width) {
1088                         case 72:
1089                         case 64:
1090                                 dimm_64bit = TRUE;
1091                                 break;
1092                         case 40:
1093                         case 32:
1094                                 dimm_32bit = TRUE;
1095                                 break;
1096                         default:
1097                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1098                                        data_width);
1099                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1100                                 break;
1101                         }
1102                 }
1103         }
1105         /* verify matching properties */
1106         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1107                 if (buf0 != buf1) {
1108                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1109                         spd_ddr_init_hang ();
1110                 }
1111         }
1113         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1114                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1115                 spd_ddr_init_hang ();
1116         }
1117         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1118                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1119         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1120                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1121         } else {
1122                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1123                 spd_ddr_init_hang ();
1124         }
1126         if (ecc_enabled == TRUE)
1127                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1128         else
1129                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1131         mtsdram(SDRAM_MCOPT1, mcopt1);
1134 /*-----------------------------------------------------------------------------+
1135  * program_codt.
1136  *-----------------------------------------------------------------------------*/
1137 static void program_codt(unsigned long *dimm_populated,
1138                          unsigned char *iic0_dimm_addr,
1139                          unsigned long num_dimm_banks)
1141         unsigned long codt;
1142         unsigned long modt0 = 0;
1143         unsigned long modt1 = 0;
1144         unsigned long modt2 = 0;
1145         unsigned long modt3 = 0;
1146         unsigned char dimm_num;
1147         unsigned char dimm_rank;
1148         unsigned char total_rank = 0;
1149         unsigned char total_dimm = 0;
1150         unsigned char dimm_type = 0;
1151         unsigned char firstSlot = 0;
1153         /*------------------------------------------------------------------
1154          * Set the SDRAM Controller On Die Termination Register
1155          *-----------------------------------------------------------------*/
1156         mfsdram(SDRAM_CODT, codt);
1157         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1158         codt |= SDRAM_CODT_IO_NMODE;
1160         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1161                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1162                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1163                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1164                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1165                                 dimm_type = SDRAM_DDR2;
1166                         } else {
1167                                 dimm_rank = dimm_rank & 0x0F;
1168                                 dimm_type = SDRAM_DDR1;
1169                         }
1171                         total_rank += dimm_rank;
1172                         total_dimm++;
1173                         if ((dimm_num == 0) && (total_dimm == 1))
1174                                 firstSlot = TRUE;
1175                         else
1176                                 firstSlot = FALSE;
1177                 }
1178         }
1179         if (dimm_type == SDRAM_DDR2) {
1180                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1181                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1182                         if (total_rank == 1) {  /* PUUU */
1183                                 codt |= CALC_ODT_R(0);
1184                                 modt0 = CALC_ODT_W(0);
1185                                 modt1 = 0x00000000;
1186                                 modt2 = 0x00000000;
1187                                 modt3 = 0x00000000;
1188                         }
1189                         if (total_rank == 2) {  /* PPUU */
1190                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1191                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1192                                 modt1 = 0x00000000;
1193                                 modt2 = 0x00000000;
1194                                 modt3 = 0x00000000;
1195                         }
1196                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1197                         if (total_rank == 1) {  /* UUPU */
1198                                 codt |= CALC_ODT_R(2);
1199                                 modt0 = 0x00000000;
1200                                 modt1 = 0x00000000;
1201                                 modt2 = CALC_ODT_W(2);
1202                                 modt3 = 0x00000000;
1203                         }
1204                         if (total_rank == 2) {  /* UUPP */
1205                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1206                                 modt0 = 0x00000000;
1207                                 modt1 = 0x00000000;
1208                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1209                                 modt3 = 0x00000000;
1210                         }
1211                 }
1212                 if (total_dimm == 2) {
1213                         if (total_rank == 2) {  /* PUPU */
1214                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1215                                 modt0 = CALC_ODT_RW(2);
1216                                 modt1 = 0x00000000;
1217                                 modt2 = CALC_ODT_RW(0);
1218                                 modt3 = 0x00000000;
1219                         }
1220                         if (total_rank == 4) {  /* PPPP */
1221                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1222                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1223                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1224                                 modt1 = 0x00000000;
1225                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1226                                 modt3 = 0x00000000;
1227                         }
1228                 }
1229         } else {
1230                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1231                 modt0 = 0x00000000;
1232                 modt1 = 0x00000000;
1233                 modt2 = 0x00000000;
1234                 modt3 = 0x00000000;
1236                 if (total_dimm == 1) {
1237                         if (total_rank == 1)
1238                                 codt |= 0x00800000;
1239                         if (total_rank == 2)
1240                                 codt |= 0x02800000;
1241                 }
1242                 if (total_dimm == 2) {
1243                         if (total_rank == 2)
1244                                 codt |= 0x08800000;
1245                         if (total_rank == 4)
1246                                 codt |= 0x2a800000;
1247                 }
1248         }
1250         debug("nb of dimm %d\n", total_dimm);
1251         debug("nb of rank %d\n", total_rank);
1252         if (total_dimm == 1)
1253                 debug("dimm in slot %d\n", firstSlot);
1255         mtsdram(SDRAM_CODT, codt);
1256         mtsdram(SDRAM_MODT0, modt0);
1257         mtsdram(SDRAM_MODT1, modt1);
1258         mtsdram(SDRAM_MODT2, modt2);
1259         mtsdram(SDRAM_MODT3, modt3);
1262 /*-----------------------------------------------------------------------------+
1263  * program_initplr.
1264  *-----------------------------------------------------------------------------*/
1265 static void program_initplr(unsigned long *dimm_populated,
1266                             unsigned char *iic0_dimm_addr,
1267                             unsigned long num_dimm_banks,
1268                             ddr_cas_id_t selected_cas,
1269                             int write_recovery)
1271         u32 cas = 0;
1272         u32 odt = 0;
1273         u32 ods = 0;
1274         u32 mr;
1275         u32 wr;
1276         u32 emr;
1277         u32 emr2;
1278         u32 emr3;
1279         int dimm_num;
1280         int total_dimm = 0;
1282         /******************************************************
1283          ** Assumption: if more than one DIMM, all DIMMs are the same
1284          **             as already checked in check_memory_type
1285          ******************************************************/
1287         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1288                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1289                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1290                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1291                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1292                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1293                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1294                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1295                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1296         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1297                 switch (selected_cas) {
1298                 case DDR_CAS_3:
1299                         cas = 3 << 4;
1300                         break;
1301                 case DDR_CAS_4:
1302                         cas = 4 << 4;
1303                         break;
1304                 case DDR_CAS_5:
1305                         cas = 5 << 4;
1306                         break;
1307                 default:
1308                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1309                         spd_ddr_init_hang ();
1310                         break;
1311                 }
1313 #if 0
1314                 /*
1315                  * ToDo - Still a problem with the write recovery:
1316                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1317                  * in the INITPLR reg to the value calculated in program_mode()
1318                  * results in not correctly working DDR2 memory (crash after
1319                  * relocation).
1320                  *
1321                  * So for now, set the write recovery to 3. This seems to work
1322                  * on the Corair module too.
1323                  *
1324                  * 2007-03-01, sr
1325                  */
1326                 switch (write_recovery) {
1327                 case 3:
1328                         wr = WRITE_RECOV_3;
1329                         break;
1330                 case 4:
1331                         wr = WRITE_RECOV_4;
1332                         break;
1333                 case 5:
1334                         wr = WRITE_RECOV_5;
1335                         break;
1336                 case 6:
1337                         wr = WRITE_RECOV_6;
1338                         break;
1339                 default:
1340                         printf("ERROR: write recovery not support (%d)", write_recovery);
1341                         spd_ddr_init_hang ();
1342                         break;
1343                 }
1344 #else
1345                 wr = WRITE_RECOV_3; /* test-only, see description above */
1346 #endif
1348                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1349                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1350                                 total_dimm++;
1351                 if (total_dimm == 1) {
1352                         odt = ODT_150_OHM;
1353                         ods = ODS_FULL;
1354                 } else if (total_dimm == 2) {
1355                         odt = ODT_75_OHM;
1356                         ods = ODS_REDUCED;
1357                 } else {
1358                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1359                         spd_ddr_init_hang ();
1360                 }
1362                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1363                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1364                 emr2 = CMD_EMR | SELECT_EMR2;
1365                 emr3 = CMD_EMR | SELECT_EMR3;
1366                 /* NOP - Wait 106 MemClk cycles */
1367                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1368                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1369                 udelay(1000);
1370                 /* precharge 4 MemClk cycles */
1371                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1372                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1373                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1374                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1375                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1376                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1377                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1378                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1379                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1380                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1381                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1382                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1383                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1384                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1385                 udelay(1000);
1386                 /* precharge 4 MemClk cycles */
1387                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1388                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1389                 /* Refresh 25 MemClk cycles */
1390                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1391                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1392                 /* Refresh 25 MemClk cycles */
1393                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1394                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1395                 /* Refresh 25 MemClk cycles */
1396                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1397                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1398                 /* Refresh 25 MemClk cycles */
1399                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1400                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1401                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1402                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1403                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1404                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1405                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1406                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1407                 /* EMR OCD Exit */
1408                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1409                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1410         } else {
1411                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1412                 spd_ddr_init_hang ();
1413         }
1416 /*------------------------------------------------------------------
1417  * This routine programs the SDRAM_MMODE register.
1418  * the selected_cas is an output parameter, that will be passed
1419  * by caller to call the above program_initplr( )
1420  *-----------------------------------------------------------------*/
1421 static void program_mode(unsigned long *dimm_populated,
1422                          unsigned char *iic0_dimm_addr,
1423                          unsigned long num_dimm_banks,
1424                          ddr_cas_id_t *selected_cas,
1425                          int *write_recovery)
1427         unsigned long dimm_num;
1428         unsigned long sdram_ddr1;
1429         unsigned long t_wr_ns;
1430         unsigned long t_wr_clk;
1431         unsigned long cas_bit;
1432         unsigned long cas_index;
1433         unsigned long sdram_freq;
1434         unsigned long ddr_check;
1435         unsigned long mmode;
1436         unsigned long tcyc_reg;
1437         unsigned long cycle_2_0_clk;
1438         unsigned long cycle_2_5_clk;
1439         unsigned long cycle_3_0_clk;
1440         unsigned long cycle_4_0_clk;
1441         unsigned long cycle_5_0_clk;
1442         unsigned long max_2_0_tcyc_ns_x_100;
1443         unsigned long max_2_5_tcyc_ns_x_100;
1444         unsigned long max_3_0_tcyc_ns_x_100;
1445         unsigned long max_4_0_tcyc_ns_x_100;
1446         unsigned long max_5_0_tcyc_ns_x_100;
1447         unsigned long cycle_time_ns_x_100[3];
1448         PPC4xx_SYS_INFO board_cfg;
1449         unsigned char cas_2_0_available;
1450         unsigned char cas_2_5_available;
1451         unsigned char cas_3_0_available;
1452         unsigned char cas_4_0_available;
1453         unsigned char cas_5_0_available;
1454         unsigned long sdr_ddrpll;
1456         /*------------------------------------------------------------------
1457          * Get the board configuration info.
1458          *-----------------------------------------------------------------*/
1459         get_sys_info(&board_cfg);
1461         mfsdr(SDR0_DDR0, sdr_ddrpll);
1462         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1463         debug("sdram_freq=%lu\n", sdram_freq);
1465         /*------------------------------------------------------------------
1466          * Handle the timing.  We need to find the worst case timing of all
1467          * the dimm modules installed.
1468          *-----------------------------------------------------------------*/
1469         t_wr_ns = 0;
1470         cas_2_0_available = TRUE;
1471         cas_2_5_available = TRUE;
1472         cas_3_0_available = TRUE;
1473         cas_4_0_available = TRUE;
1474         cas_5_0_available = TRUE;
1475         max_2_0_tcyc_ns_x_100 = 10;
1476         max_2_5_tcyc_ns_x_100 = 10;
1477         max_3_0_tcyc_ns_x_100 = 10;
1478         max_4_0_tcyc_ns_x_100 = 10;
1479         max_5_0_tcyc_ns_x_100 = 10;
1480         sdram_ddr1 = TRUE;
1482         /* loop through all the DIMM slots on the board */
1483         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1484                 /* If a dimm is installed in a particular slot ... */
1485                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1486                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1487                                 sdram_ddr1 = TRUE;
1488                         else
1489                                 sdram_ddr1 = FALSE;
1491                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1492                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1494                         /* For a particular DIMM, grab the three CAS values it supports */
1495                         for (cas_index = 0; cas_index < 3; cas_index++) {
1496                                 switch (cas_index) {
1497                                 case 0:
1498                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1499                                         break;
1500                                 case 1:
1501                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1502                                         break;
1503                                 default:
1504                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1505                                         break;
1506                                 }
1508                                 if ((tcyc_reg & 0x0F) >= 10) {
1509                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1510                                                 /* Convert from hex to decimal */
1511                                                 cycle_time_ns_x_100[cas_index] =
1512                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1513                                         } else {
1514                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1515                                                        "in slot %d\n", (unsigned int)dimm_num);
1516                                                 spd_ddr_init_hang ();
1517                                         }
1518                                 } else {
1519                                         /* Convert from hex to decimal */
1520                                         cycle_time_ns_x_100[cas_index] =
1521                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1522                                                 ((tcyc_reg & 0x0F)*10);
1523                                 }
1524                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1525                                       cycle_time_ns_x_100[cas_index]);
1526                         }
1528                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1529                         /* supported for a particular DIMM. */
1530                         cas_index = 0;
1532                         if (sdram_ddr1) {
1533                                 /*
1534                                  * DDR devices use the following bitmask for CAS latency:
1535                                  *  Bit   7    6    5    4    3    2    1    0
1536                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1537                                  */
1538                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1539                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1540                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1541                                                                     cycle_time_ns_x_100[cas_index]);
1542                                         cas_index++;
1543                                 } else {
1544                                         if (cas_index != 0)
1545                                                 cas_index++;
1546                                         cas_4_0_available = FALSE;
1547                                 }
1549                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1550                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1551                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1552                                                                     cycle_time_ns_x_100[cas_index]);
1553                                         cas_index++;
1554                                 } else {
1555                                         if (cas_index != 0)
1556                                                 cas_index++;
1557                                         cas_3_0_available = FALSE;
1558                                 }
1560                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1561                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1562                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1563                                                                     cycle_time_ns_x_100[cas_index]);
1564                                         cas_index++;
1565                                 } else {
1566                                         if (cas_index != 0)
1567                                                 cas_index++;
1568                                         cas_2_5_available = FALSE;
1569                                 }
1571                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1572                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1573                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1574                                                                     cycle_time_ns_x_100[cas_index]);
1575                                         cas_index++;
1576                                 } else {
1577                                         if (cas_index != 0)
1578                                                 cas_index++;
1579                                         cas_2_0_available = FALSE;
1580                                 }
1581                         } else {
1582                                 /*
1583                                  * DDR2 devices use the following bitmask for CAS latency:
1584                                  *  Bit   7    6    5    4    3    2    1    0
1585                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1586                                  */
1587                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1588                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1589                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1590                                                                     cycle_time_ns_x_100[cas_index]);
1591                                         cas_index++;
1592                                 } else {
1593                                         if (cas_index != 0)
1594                                                 cas_index++;
1595                                         cas_5_0_available = FALSE;
1596                                 }
1598                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1599                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1600                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1601                                                                     cycle_time_ns_x_100[cas_index]);
1602                                         cas_index++;
1603                                 } else {
1604                                         if (cas_index != 0)
1605                                                 cas_index++;
1606                                         cas_4_0_available = FALSE;
1607                                 }
1609                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1610                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1611                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1612                                                                     cycle_time_ns_x_100[cas_index]);
1613                                         cas_index++;
1614                                 } else {
1615                                         if (cas_index != 0)
1616                                                 cas_index++;
1617                                         cas_3_0_available = FALSE;
1618                                 }
1619                         }
1620                 }
1621         }
1623         /*------------------------------------------------------------------
1624          * Set the SDRAM mode, SDRAM_MMODE
1625          *-----------------------------------------------------------------*/
1626         mfsdram(SDRAM_MMODE, mmode);
1627         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1629         /* add 10 here because of rounding problems */
1630         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1631         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1632         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1633         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1634         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1635         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1636         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1637         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1639         if (sdram_ddr1 == TRUE) { /* DDR1 */
1640                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1641                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1642                         *selected_cas = DDR_CAS_2;
1643                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1644                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1645                         *selected_cas = DDR_CAS_2_5;
1646                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1647                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1648                         *selected_cas = DDR_CAS_3;
1649                 } else {
1650                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1651                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1652                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1653                         spd_ddr_init_hang ();
1654                 }
1655         } else { /* DDR2 */
1656                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1657                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1658                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1659                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1660                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1661                         *selected_cas = DDR_CAS_3;
1662                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1663                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1664                         *selected_cas = DDR_CAS_4;
1665                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1666                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1667                         *selected_cas = DDR_CAS_5;
1668                 } else {
1669                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1670                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1671                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1672                         printf("cas3=%d cas4=%d cas5=%d\n",
1673                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1674                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1675                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1676                         spd_ddr_init_hang ();
1677                 }
1678         }
1680         if (sdram_ddr1 == TRUE)
1681                 mmode |= SDRAM_MMODE_WR_DDR1;
1682         else {
1684                 /* loop through all the DIMM slots on the board */
1685                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1686                         /* If a dimm is installed in a particular slot ... */
1687                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1688                                 t_wr_ns = max(t_wr_ns,
1689                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1690                 }
1692                 /*
1693                  * convert from nanoseconds to ddr clocks
1694                  * round up if necessary
1695                  */
1696                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1697                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1698                 if (sdram_freq != ddr_check)
1699                         t_wr_clk++;
1701                 switch (t_wr_clk) {
1702                 case 0:
1703                 case 1:
1704                 case 2:
1705                 case 3:
1706                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1707                         break;
1708                 case 4:
1709                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1710                         break;
1711                 case 5:
1712                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1713                         break;
1714                 default:
1715                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1716                         break;
1717                 }
1718                 *write_recovery = t_wr_clk;
1719         }
1721         debug("CAS latency = %d\n", *selected_cas);
1722         debug("Write recovery = %d\n", *write_recovery);
1724         mtsdram(SDRAM_MMODE, mmode);
1727 /*-----------------------------------------------------------------------------+
1728  * program_rtr.
1729  *-----------------------------------------------------------------------------*/
1730 static void program_rtr(unsigned long *dimm_populated,
1731                         unsigned char *iic0_dimm_addr,
1732                         unsigned long num_dimm_banks)
1734         PPC4xx_SYS_INFO board_cfg;
1735         unsigned long max_refresh_rate;
1736         unsigned long dimm_num;
1737         unsigned long refresh_rate_type;
1738         unsigned long refresh_rate;
1739         unsigned long rint;
1740         unsigned long sdram_freq;
1741         unsigned long sdr_ddrpll;
1742         unsigned long val;
1744         /*------------------------------------------------------------------
1745          * Get the board configuration info.
1746          *-----------------------------------------------------------------*/
1747         get_sys_info(&board_cfg);
1749         /*------------------------------------------------------------------
1750          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1751          *-----------------------------------------------------------------*/
1752         mfsdr(SDR0_DDR0, sdr_ddrpll);
1753         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1755         max_refresh_rate = 0;
1756         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1757                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1759                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1760                         refresh_rate_type &= 0x7F;
1761                         switch (refresh_rate_type) {
1762                         case 0:
1763                                 refresh_rate =  15625;
1764                                 break;
1765                         case 1:
1766                                 refresh_rate =   3906;
1767                                 break;
1768                         case 2:
1769                                 refresh_rate =   7812;
1770                                 break;
1771                         case 3:
1772                                 refresh_rate =  31250;
1773                                 break;
1774                         case 4:
1775                                 refresh_rate =  62500;
1776                                 break;
1777                         case 5:
1778                                 refresh_rate = 125000;
1779                                 break;
1780                         default:
1781                                 refresh_rate = 0;
1782                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1783                                        (unsigned int)dimm_num);
1784                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1785                                 spd_ddr_init_hang ();
1786                                 break;
1787                         }
1789                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1790                 }
1791         }
1793         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1794         mfsdram(SDRAM_RTR, val);
1795         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1796                 (SDRAM_RTR_RINT_ENCODE(rint)));
1799 /*------------------------------------------------------------------
1800  * This routine programs the SDRAM_TRx registers.
1801  *-----------------------------------------------------------------*/
1802 static void program_tr(unsigned long *dimm_populated,
1803                        unsigned char *iic0_dimm_addr,
1804                        unsigned long num_dimm_banks)
1806         unsigned long dimm_num;
1807         unsigned long sdram_ddr1;
1808         unsigned long t_rp_ns;
1809         unsigned long t_rcd_ns;
1810         unsigned long t_rrd_ns;
1811         unsigned long t_ras_ns;
1812         unsigned long t_rc_ns;
1813         unsigned long t_rfc_ns;
1814         unsigned long t_wpc_ns;
1815         unsigned long t_wtr_ns;
1816         unsigned long t_rpc_ns;
1817         unsigned long t_rp_clk;
1818         unsigned long t_rcd_clk;
1819         unsigned long t_rrd_clk;
1820         unsigned long t_ras_clk;
1821         unsigned long t_rc_clk;
1822         unsigned long t_rfc_clk;
1823         unsigned long t_wpc_clk;
1824         unsigned long t_wtr_clk;
1825         unsigned long t_rpc_clk;
1826         unsigned long sdtr1, sdtr2, sdtr3;
1827         unsigned long ddr_check;
1828         unsigned long sdram_freq;
1829         unsigned long sdr_ddrpll;
1831         PPC4xx_SYS_INFO board_cfg;
1833         /*------------------------------------------------------------------
1834          * Get the board configuration info.
1835          *-----------------------------------------------------------------*/
1836         get_sys_info(&board_cfg);
1838         mfsdr(SDR0_DDR0, sdr_ddrpll);
1839         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1841         /*------------------------------------------------------------------
1842          * Handle the timing.  We need to find the worst case timing of all
1843          * the dimm modules installed.
1844          *-----------------------------------------------------------------*/
1845         t_rp_ns = 0;
1846         t_rrd_ns = 0;
1847         t_rcd_ns = 0;
1848         t_ras_ns = 0;
1849         t_rc_ns = 0;
1850         t_rfc_ns = 0;
1851         t_wpc_ns = 0;
1852         t_wtr_ns = 0;
1853         t_rpc_ns = 0;
1854         sdram_ddr1 = TRUE;
1856         /* loop through all the DIMM slots on the board */
1857         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1858                 /* If a dimm is installed in a particular slot ... */
1859                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1860                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1861                                 sdram_ddr1 = TRUE;
1862                         else
1863                                 sdram_ddr1 = FALSE;
1865                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1866                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1867                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1868                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1869                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1870                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1871                 }
1872         }
1874         /*------------------------------------------------------------------
1875          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1876          *-----------------------------------------------------------------*/
1877         mfsdram(SDRAM_SDTR1, sdtr1);
1878         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1879                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1881         /* default values */
1882         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1883         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1885         /* normal operations */
1886         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1887         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1889         mtsdram(SDRAM_SDTR1, sdtr1);
1891         /*------------------------------------------------------------------
1892          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1893          *-----------------------------------------------------------------*/
1894         mfsdram(SDRAM_SDTR2, sdtr2);
1895         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1896                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1897                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1898                    SDRAM_SDTR2_RRD_MASK);
1900         /*
1901          * convert t_rcd from nanoseconds to ddr clocks
1902          * round up if necessary
1903          */
1904         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1905         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1906         if (sdram_freq != ddr_check)
1907                 t_rcd_clk++;
1909         switch (t_rcd_clk) {
1910         case 0:
1911         case 1:
1912                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1913                 break;
1914         case 2:
1915                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1916                 break;
1917         case 3:
1918                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1919                 break;
1920         case 4:
1921                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1922                 break;
1923         default:
1924                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1925                 break;
1926         }
1928         if (sdram_ddr1 == TRUE) { /* DDR1 */
1929                 if (sdram_freq < 200000000) {
1930                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1931                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1932                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1933                 } else {
1934                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1935                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1936                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1937                 }
1938         } else { /* DDR2 */
1939                 /* loop through all the DIMM slots on the board */
1940                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1941                         /* If a dimm is installed in a particular slot ... */
1942                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1943                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1944                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1945                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1946                         }
1947                 }
1949                 /*
1950                  * convert from nanoseconds to ddr clocks
1951                  * round up if necessary
1952                  */
1953                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1954                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1955                 if (sdram_freq != ddr_check)
1956                         t_wpc_clk++;
1958                 switch (t_wpc_clk) {
1959                 case 0:
1960                 case 1:
1961                 case 2:
1962                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1963                         break;
1964                 case 3:
1965                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1966                         break;
1967                 case 4:
1968                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1969                         break;
1970                 case 5:
1971                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1972                         break;
1973                 default:
1974                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1975                         break;
1976                 }
1978                 /*
1979                  * convert from nanoseconds to ddr clocks
1980                  * round up if necessary
1981                  */
1982                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1983                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1984                 if (sdram_freq != ddr_check)
1985                         t_wtr_clk++;
1987                 switch (t_wtr_clk) {
1988                 case 0:
1989                 case 1:
1990                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1991                         break;
1992                 case 2:
1993                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1994                         break;
1995                 case 3:
1996                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1997                         break;
1998                 default:
1999                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
2000                         break;
2001                 }
2003                 /*
2004                  * convert from nanoseconds to ddr clocks
2005                  * round up if necessary
2006                  */
2007                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2008                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2009                 if (sdram_freq != ddr_check)
2010                         t_rpc_clk++;
2012                 switch (t_rpc_clk) {
2013                 case 0:
2014                 case 1:
2015                 case 2:
2016                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2017                         break;
2018                 case 3:
2019                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2020                         break;
2021                 default:
2022                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2023                         break;
2024                 }
2025         }
2027         /* default value */
2028         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2030         /*
2031          * convert t_rrd from nanoseconds to ddr clocks
2032          * round up if necessary
2033          */
2034         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2035         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2036         if (sdram_freq != ddr_check)
2037                 t_rrd_clk++;
2039         if (t_rrd_clk == 3)
2040                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2041         else
2042                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2044         /*
2045          * convert t_rp from nanoseconds to ddr clocks
2046          * round up if necessary
2047          */
2048         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2049         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2050         if (sdram_freq != ddr_check)
2051                 t_rp_clk++;
2053         switch (t_rp_clk) {
2054         case 0:
2055         case 1:
2056         case 2:
2057         case 3:
2058                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2059                 break;
2060         case 4:
2061                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2062                 break;
2063         case 5:
2064                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2065                 break;
2066         case 6:
2067                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2068                 break;
2069         default:
2070                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2071                 break;
2072         }
2074         mtsdram(SDRAM_SDTR2, sdtr2);
2076         /*------------------------------------------------------------------
2077          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2078          *-----------------------------------------------------------------*/
2079         mfsdram(SDRAM_SDTR3, sdtr3);
2080         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2081                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2083         /*
2084          * convert t_ras from nanoseconds to ddr clocks
2085          * round up if necessary
2086          */
2087         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2088         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2089         if (sdram_freq != ddr_check)
2090                 t_ras_clk++;
2092         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2094         /*
2095          * convert t_rc from nanoseconds to ddr clocks
2096          * round up if necessary
2097          */
2098         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2099         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2100         if (sdram_freq != ddr_check)
2101                 t_rc_clk++;
2103         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2105         /* default xcs value */
2106         sdtr3 |= SDRAM_SDTR3_XCS;
2108         /*
2109          * convert t_rfc from nanoseconds to ddr clocks
2110          * round up if necessary
2111          */
2112         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2113         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2114         if (sdram_freq != ddr_check)
2115                 t_rfc_clk++;
2117         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2119         mtsdram(SDRAM_SDTR3, sdtr3);
2122 /*-----------------------------------------------------------------------------+
2123  * program_bxcf.
2124  *-----------------------------------------------------------------------------*/
2125 static void program_bxcf(unsigned long *dimm_populated,
2126                          unsigned char *iic0_dimm_addr,
2127                          unsigned long num_dimm_banks)
2129         unsigned long dimm_num;
2130         unsigned long num_col_addr;
2131         unsigned long num_ranks;
2132         unsigned long num_banks;
2133         unsigned long mode;
2134         unsigned long ind_rank;
2135         unsigned long ind;
2136         unsigned long ind_bank;
2137         unsigned long bank_0_populated;
2139         /*------------------------------------------------------------------
2140          * Set the BxCF regs.  First, wipe out the bank config registers.
2141          *-----------------------------------------------------------------*/
2142         mtsdram(SDRAM_MB0CF, 0x00000000);
2143         mtsdram(SDRAM_MB1CF, 0x00000000);
2144         mtsdram(SDRAM_MB2CF, 0x00000000);
2145         mtsdram(SDRAM_MB3CF, 0x00000000);
2147         mode = SDRAM_BXCF_M_BE_ENABLE;
2149         bank_0_populated = 0;
2151         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2152                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2153                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2154                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2155                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2156                                 num_ranks = (num_ranks & 0x0F) +1;
2157                         else
2158                                 num_ranks = num_ranks & 0x0F;
2160                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2162                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2163                                 if (num_banks == 4)
2164                                         ind = 0;
2165                                 else
2166                                         ind = 5 << 8;
2167                                 switch (num_col_addr) {
2168                                 case 0x08:
2169                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2170                                         break;
2171                                 case 0x09:
2172                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2173                                         break;
2174                                 case 0x0A:
2175                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2176                                         break;
2177                                 case 0x0B:
2178                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2179                                         break;
2180                                 case 0x0C:
2181                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2182                                         break;
2183                                 default:
2184                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2185                                                (unsigned int)dimm_num);
2186                                         printf("ERROR: Unsupported value for number of "
2187                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2188                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2189                                         spd_ddr_init_hang ();
2190                                 }
2191                         }
2193                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2194                                 bank_0_populated = 1;
2196                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2197                                 mtsdram(SDRAM_MB0CF +
2198                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2199                                         mode);
2200                         }
2201                 }
2202         }
2205 /*------------------------------------------------------------------
2206  * program memory queue.
2207  *-----------------------------------------------------------------*/
2208 static void program_memory_queue(unsigned long *dimm_populated,
2209                                  unsigned char *iic0_dimm_addr,
2210                                  unsigned long num_dimm_banks)
2212         unsigned long dimm_num;
2213         phys_size_t rank_base_addr;
2214         unsigned long rank_reg;
2215         phys_size_t rank_size_bytes;
2216         unsigned long rank_size_id;
2217         unsigned long num_ranks;
2218         unsigned long baseadd_size;
2219         unsigned long i;
2220         unsigned long bank_0_populated = 0;
2221         phys_size_t total_size = 0;
2223         /*------------------------------------------------------------------
2224          * Reset the rank_base_address.
2225          *-----------------------------------------------------------------*/
2226         rank_reg   = SDRAM_R0BAS;
2228         rank_base_addr = 0x00000000;
2230         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2231                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2232                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2233                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2234                                 num_ranks = (num_ranks & 0x0F) + 1;
2235                         else
2236                                 num_ranks = num_ranks & 0x0F;
2238                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2240                         /*------------------------------------------------------------------
2241                          * Set the sizes
2242                          *-----------------------------------------------------------------*/
2243                         baseadd_size = 0;
2244                         switch (rank_size_id) {
2245                         case 0x01:
2246                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2247                                 total_size = 1024;
2248                                 break;
2249                         case 0x02:
2250                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2251                                 total_size = 2048;
2252                                 break;
2253                         case 0x04:
2254                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2255                                 total_size = 4096;
2256                                 break;
2257                         case 0x08:
2258                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2259                                 total_size = 32;
2260                                 break;
2261                         case 0x10:
2262                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2263                                 total_size = 64;
2264                                 break;
2265                         case 0x20:
2266                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2267                                 total_size = 128;
2268                                 break;
2269                         case 0x40:
2270                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2271                                 total_size = 256;
2272                                 break;
2273                         case 0x80:
2274                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2275                                 total_size = 512;
2276                                 break;
2277                         default:
2278                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2279                                        (unsigned int)dimm_num);
2280                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2281                                        (unsigned int)rank_size_id);
2282                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2283                                 spd_ddr_init_hang ();
2284                         }
2285                         rank_size_bytes = total_size << 20;
2287                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2288                                 bank_0_populated = 1;
2290                         for (i = 0; i < num_ranks; i++) {
2291                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2292                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2293                                            baseadd_size));
2294                                 rank_base_addr += rank_size_bytes;
2295                         }
2296                 }
2297         }
2299 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2300     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2301     defined(CONFIG_460SX)
2302         /*
2303          * Enable high bandwidth access
2304          * This is currently not used, but with this setup
2305          * it is possible to use it later on in e.g. the Linux
2306          * EMAC driver for performance gain.
2307          */
2308         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2309         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2311         /*
2312          * Set optimal value for Memory Queue HB/LL Configuration registers
2313          */
2314         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2315               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2316               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2317         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2318               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2319               SDRAM_CONF1LL_RPLM);
2320         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2321 #endif
2324 #ifdef CONFIG_DDR_ECC
2325 /*-----------------------------------------------------------------------------+
2326  * program_ecc.
2327  *-----------------------------------------------------------------------------*/
2328 static void program_ecc(unsigned long *dimm_populated,
2329                         unsigned char *iic0_dimm_addr,
2330                         unsigned long num_dimm_banks,
2331                         unsigned long tlb_word2_i_value)
2333         unsigned long dimm_num;
2334         unsigned long ecc;
2336         ecc = 0;
2337         /* loop through all the DIMM slots on the board */
2338         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2339                 /* If a dimm is installed in a particular slot ... */
2340                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2341                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2342         }
2343         if (ecc == 0)
2344                 return;
2346         do_program_ecc(tlb_word2_i_value);
2348 #endif
2350 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2351 /*-----------------------------------------------------------------------------+
2352  * program_DQS_calibration.
2353  *-----------------------------------------------------------------------------*/
2354 static void program_DQS_calibration(unsigned long *dimm_populated,
2355                                     unsigned char *iic0_dimm_addr,
2356                                     unsigned long num_dimm_banks)
2358         unsigned long val;
2360 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2361         mtsdram(SDRAM_RQDC, 0x80000037);
2362         mtsdram(SDRAM_RDCC, 0x40000000);
2363         mtsdram(SDRAM_RFDC, 0x000001DF);
2365         test();
2366 #else
2367         /*------------------------------------------------------------------
2368          * Program RDCC register
2369          * Read sample cycle auto-update enable
2370          *-----------------------------------------------------------------*/
2372         mfsdram(SDRAM_RDCC, val);
2373         mtsdram(SDRAM_RDCC,
2374                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2375                 | SDRAM_RDCC_RSAE_ENABLE);
2377         /*------------------------------------------------------------------
2378          * Program RQDC register
2379          * Internal DQS delay mechanism enable
2380          *-----------------------------------------------------------------*/
2381         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2383         /*------------------------------------------------------------------
2384          * Program RFDC register
2385          * Set Feedback Fractional Oversample
2386          * Auto-detect read sample cycle enable
2387          * Set RFOS to 1/4 of memclk cycle (0x3f)
2388          *-----------------------------------------------------------------*/
2389         mfsdram(SDRAM_RFDC, val);
2390         mtsdram(SDRAM_RFDC,
2391                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2392                          SDRAM_RFDC_RFFD_MASK))
2393                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2394                    SDRAM_RFDC_RFFD_ENCODE(0)));
2396         DQS_calibration_process();
2397 #endif
2400 static int short_mem_test(void)
2402         u32 *membase;
2403         u32 bxcr_num;
2404         u32 bxcf;
2405         int i;
2406         int j;
2407         phys_size_t base_addr;
2408         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2409                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2410                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2411                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2412                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2413                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2414                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2415                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2416                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2417                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2418                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2419                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2420                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2421                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2422                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2423                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2424                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2425         int l;
2427         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2428                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2430                 /* Banks enabled */
2431                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2432                         /* Bank is enabled */
2434                         /*
2435                          * Only run test on accessable memory (below 2GB)
2436                          */
2437                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2438                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2439                                 continue;
2441                         /*------------------------------------------------------------------
2442                          * Run the short memory test.
2443                          *-----------------------------------------------------------------*/
2444                         membase = (u32 *)(u32)base_addr;
2446                         for (i = 0; i < NUMMEMTESTS; i++) {
2447                                 for (j = 0; j < NUMMEMWORDS; j++) {
2448                                         membase[j] = test[i][j];
2449                                         ppcDcbf((u32)&(membase[j]));
2450                                 }
2451                                 sync();
2452                                 for (l=0; l<NUMLOOPS; l++) {
2453                                         for (j = 0; j < NUMMEMWORDS; j++) {
2454                                                 if (membase[j] != test[i][j]) {
2455                                                         ppcDcbf((u32)&(membase[j]));
2456                                                         return 0;
2457                                                 }
2458                                                 ppcDcbf((u32)&(membase[j]));
2459                                         }
2460                                         sync();
2461                                 }
2462                         }
2463                 }       /* if bank enabled */
2464         }               /* for bxcf_num */
2466         return 1;
2469 #ifndef HARD_CODED_DQS
2470 /*-----------------------------------------------------------------------------+
2471  * DQS_calibration_process.
2472  *-----------------------------------------------------------------------------*/
2473 static void DQS_calibration_process(void)
2475         unsigned long rfdc_reg;
2476         unsigned long rffd;
2477         unsigned long val;
2478         long rffd_average;
2479         long max_start;
2480         unsigned long dlycal;
2481         unsigned long dly_val;
2482         unsigned long max_pass_length;
2483         unsigned long current_pass_length;
2484         unsigned long current_fail_length;
2485         unsigned long current_start;
2486         long max_end;
2487         unsigned char fail_found;
2488         unsigned char pass_found;
2489 #if !defined(CONFIG_DDR_RQDC_FIXED)
2490         int window_found;
2491         u32 rqdc_reg;
2492         u32 rqfd;
2493         u32 rqfd_start;
2494         u32 rqfd_average;
2495         int loopi = 0;
2496         char str[] = "Auto calibration -";
2497         char slash[] = "\\|/-\\|/-";
2499         /*------------------------------------------------------------------
2500          * Test to determine the best read clock delay tuning bits.
2501          *
2502          * Before the DDR controller can be used, the read clock delay needs to be
2503          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2504          * This value cannot be hardcoded into the program because it changes
2505          * depending on the board's setup and environment.
2506          * To do this, all delay values are tested to see if they
2507          * work or not.  By doing this, you get groups of fails with groups of
2508          * passing values.  The idea is to find the start and end of a passing
2509          * window and take the center of it to use as the read clock delay.
2510          *
2511          * A failure has to be seen first so that when we hit a pass, we know
2512          * that it is truely the start of the window.  If we get passing values
2513          * to start off with, we don't know if we are at the start of the window.
2514          *
2515          * The code assumes that a failure will always be found.
2516          * If a failure is not found, there is no easy way to get the middle
2517          * of the passing window.  I guess we can pretty much pick any value
2518          * but some values will be better than others.  Since the lowest speed
2519          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2520          * from experimentation it is safe to say you will always have a failure.
2521          *-----------------------------------------------------------------*/
2523         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2524         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2526         puts(str);
2528 calibration_loop:
2529         mfsdram(SDRAM_RQDC, rqdc_reg);
2530         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2531                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2532 #else /* CONFIG_DDR_RQDC_FIXED */
2533         /*
2534          * On Katmai the complete auto-calibration somehow doesn't seem to
2535          * produce the best results, meaning optimal values for RQFD/RFFD.
2536          * This was discovered by GDA using a high bandwidth scope,
2537          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2538          * so now on Katmai "only" RFFD is auto-calibrated.
2539          */
2540         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2541 #endif /* CONFIG_DDR_RQDC_FIXED */
2543         max_start = 0;
2545         max_pass_length = 0;
2546         max_start = 0;
2547         max_end = 0;
2548         current_pass_length = 0;
2549         current_fail_length = 0;
2550         current_start = 0;
2551         fail_found = FALSE;
2552         pass_found = FALSE;
2554         /*
2555          * get the delay line calibration register value
2556          */
2557         mfsdram(SDRAM_DLCR, dlycal);
2558         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2560         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2561                 mfsdram(SDRAM_RFDC, rfdc_reg);
2562                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2564                 /*------------------------------------------------------------------
2565                  * Set the timing reg for the test.
2566                  *-----------------------------------------------------------------*/
2567                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2569                 /*------------------------------------------------------------------
2570                  * See if the rffd value passed.
2571                  *-----------------------------------------------------------------*/
2572                 if (short_mem_test()) {
2573                         if (fail_found == TRUE) {
2574                                 pass_found = TRUE;
2575                                 if (current_pass_length == 0)
2576                                         current_start = rffd;
2578                                 current_fail_length = 0;
2579                                 current_pass_length++;
2581                                 if (current_pass_length > max_pass_length) {
2582                                         max_pass_length = current_pass_length;
2583                                         max_start = current_start;
2584                                         max_end = rffd;
2585                                 }
2586                         }
2587                 } else {
2588                         current_pass_length = 0;
2589                         current_fail_length++;
2591                         if (current_fail_length >= (dly_val >> 2)) {
2592                                 if (fail_found == FALSE) {
2593                                         fail_found = TRUE;
2594                                 } else if (pass_found == TRUE) {
2595                                         break;
2596                                 }
2597                         }
2598                 }
2599         }               /* for rffd */
2601         /*------------------------------------------------------------------
2602          * Set the average RFFD value
2603          *-----------------------------------------------------------------*/
2604         rffd_average = ((max_start + max_end) >> 1);
2606         if (rffd_average < 0)
2607                 rffd_average = 0;
2609         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2610                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2611         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2612         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2614 #if !defined(CONFIG_DDR_RQDC_FIXED)
2615         max_pass_length = 0;
2616         max_start = 0;
2617         max_end = 0;
2618         current_pass_length = 0;
2619         current_fail_length = 0;
2620         current_start = 0;
2621         window_found = FALSE;
2622         fail_found = FALSE;
2623         pass_found = FALSE;
2625         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2626                 mfsdram(SDRAM_RQDC, rqdc_reg);
2627                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2629                 /*------------------------------------------------------------------
2630                  * Set the timing reg for the test.
2631                  *-----------------------------------------------------------------*/
2632                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2634                 /*------------------------------------------------------------------
2635                  * See if the rffd value passed.
2636                  *-----------------------------------------------------------------*/
2637                 if (short_mem_test()) {
2638                         if (fail_found == TRUE) {
2639                                 pass_found = TRUE;
2640                                 if (current_pass_length == 0)
2641                                         current_start = rqfd;
2643                                 current_fail_length = 0;
2644                                 current_pass_length++;
2646                                 if (current_pass_length > max_pass_length) {
2647                                         max_pass_length = current_pass_length;
2648                                         max_start = current_start;
2649                                         max_end = rqfd;
2650                                 }
2651                         }
2652                 } else {
2653                         current_pass_length = 0;
2654                         current_fail_length++;
2656                         if (fail_found == FALSE) {
2657                                 fail_found = TRUE;
2658                         } else if (pass_found == TRUE) {
2659                                 window_found = TRUE;
2660                                 break;
2661                         }
2662                 }
2663         }
2665         rqfd_average = ((max_start + max_end) >> 1);
2667         /*------------------------------------------------------------------
2668          * Make sure we found the valid read passing window.  Halt if not
2669          *-----------------------------------------------------------------*/
2670         if (window_found == FALSE) {
2671                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2672                         putc('\b');
2673                         putc(slash[loopi++ % 8]);
2675                         /* try again from with a different RQFD start value */
2676                         rqfd_start++;
2677                         goto calibration_loop;
2678                 }
2680                 printf("\nERROR: Cannot determine a common read delay for the "
2681                        "DIMM(s) installed.\n");
2682                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2683                 ppc4xx_ibm_ddr2_register_dump();
2684                 spd_ddr_init_hang ();
2685         }
2687         if (rqfd_average < 0)
2688                 rqfd_average = 0;
2690         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2691                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2693         mtsdram(SDRAM_RQDC,
2694                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2695                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2697         blank_string(strlen(str));
2698 #endif /* CONFIG_DDR_RQDC_FIXED */
2700         mfsdram(SDRAM_DLCR, val);
2701         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2702         mfsdram(SDRAM_RQDC, val);
2703         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2704         mfsdram(SDRAM_RFDC, val);
2705         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2706         mfsdram(SDRAM_RDCC, val);
2707         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2709 #else /* calibration test with hardvalues */
2710 /*-----------------------------------------------------------------------------+
2711  * DQS_calibration_process.
2712  *-----------------------------------------------------------------------------*/
2713 static void test(void)
2715         unsigned long dimm_num;
2716         unsigned long ecc_temp;
2717         unsigned long i, j;
2718         unsigned long *membase;
2719         unsigned long bxcf[MAXRANKS];
2720         unsigned long val;
2721         char window_found;
2722         char begin_found[MAXDIMMS];
2723         char end_found[MAXDIMMS];
2724         char search_end[MAXDIMMS];
2725         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2726                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2727                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2728                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2729                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2730                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2731                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2732                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2733                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2734                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2735                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2736                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2737                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2738                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2739                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2740                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2741                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2743         /*------------------------------------------------------------------
2744          * Test to determine the best read clock delay tuning bits.
2745          *
2746          * Before the DDR controller can be used, the read clock delay needs to be
2747          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2748          * This value cannot be hardcoded into the program because it changes
2749          * depending on the board's setup and environment.
2750          * To do this, all delay values are tested to see if they
2751          * work or not.  By doing this, you get groups of fails with groups of
2752          * passing values.  The idea is to find the start and end of a passing
2753          * window and take the center of it to use as the read clock delay.
2754          *
2755          * A failure has to be seen first so that when we hit a pass, we know
2756          * that it is truely the start of the window.  If we get passing values
2757          * to start off with, we don't know if we are at the start of the window.
2758          *
2759          * The code assumes that a failure will always be found.
2760          * If a failure is not found, there is no easy way to get the middle
2761          * of the passing window.  I guess we can pretty much pick any value
2762          * but some values will be better than others.  Since the lowest speed
2763          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2764          * from experimentation it is safe to say you will always have a failure.
2765          *-----------------------------------------------------------------*/
2766         mfsdram(SDRAM_MCOPT1, ecc_temp);
2767         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2768         mfsdram(SDRAM_MCOPT1, val);
2769         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2770                 SDRAM_MCOPT1_MCHK_NON);
2772         window_found = FALSE;
2773         begin_found[0] = FALSE;
2774         end_found[0] = FALSE;
2775         search_end[0] = FALSE;
2776         begin_found[1] = FALSE;
2777       &n