arch/powerpc/include/asm/fsl_ddr_sdram.h

   1 /*
   2  * Copyright 2008-2009 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef FSL_DDR_MEMCTL_H
  10 #define FSL_DDR_MEMCTL_H
  11
  12 /*
  13  * Pick a basic DDR Technology.
  14  */
  15 #include <ddr_spd.h>
  16
  17 #define SDRAM_TYPE_DDR1    2
  18 #define SDRAM_TYPE_DDR2    3
  19 #define SDRAM_TYPE_LPDDR1  6
  20 #define SDRAM_TYPE_DDR3    7
  21
  22 #define DDR_BL4         4       /* burst length 4 */
  23 #define DDR_BC4         DDR_BL4 /* burst chop for ddr3 */
  24 #define DDR_OTF         6       /* on-the-fly BC4 and BL8 */
  25 #define DDR_BL8         8       /* burst length 8 */
  26
  27 #if defined(CONFIG_FSL_DDR1)
  28 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (1)
  29 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
  30 #ifndef CONFIG_FSL_SDRAM_TYPE
  31 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR1
  32 #endif
  33 #elif defined(CONFIG_FSL_DDR2)
  34 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (3)
  35 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
  36 #ifndef CONFIG_FSL_SDRAM_TYPE
  37 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR2
  38 #endif
  39 #elif defined(CONFIG_FSL_DDR3)
  40 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (3)     /* FIXME */
  41 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
  42 #ifndef CONFIG_FSL_SDRAM_TYPE
  43 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR3
  44 #endif
  45 #endif  /* #if defined(CONFIG_FSL_DDR1) */
  46
  47 /* define bank(chip select) interleaving mode */
  48 #define FSL_DDR_CS0_CS1                 0x40
  49 #define FSL_DDR_CS2_CS3                 0x20
  50 #define FSL_DDR_CS0_CS1_AND_CS2_CS3     (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
  51 #define FSL_DDR_CS0_CS1_CS2_CS3         (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
  52
  53 /* define memory controller interleaving mode */
  54 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
  55 #define FSL_DDR_PAGE_INTERLEAVING       0x1
  56 #define FSL_DDR_BANK_INTERLEAVING       0x2
  57 #define FSL_DDR_SUPERBANK_INTERLEAVING  0x3
  58
  59 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  60  */
  61 #define SDRAM_CFG_MEM_EN                0x80000000
  62 #define SDRAM_CFG_SREN                  0x40000000
  63 #define SDRAM_CFG_ECC_EN                0x20000000
  64 #define SDRAM_CFG_RD_EN                 0x10000000
  65 #define SDRAM_CFG_SDRAM_TYPE_DDR1       0x02000000
  66 #define SDRAM_CFG_SDRAM_TYPE_DDR2       0x03000000
  67 #define SDRAM_CFG_SDRAM_TYPE_MASK       0x07000000
  68 #define SDRAM_CFG_SDRAM_TYPE_SHIFT      24
  69 #define SDRAM_CFG_DYN_PWR               0x00200000
  70 #define SDRAM_CFG_32_BE                 0x00080000
  71 #define SDRAM_CFG_8_BE                  0x00040000
  72 #define SDRAM_CFG_NCAP                  0x00020000
  73 #define SDRAM_CFG_2T_EN                 0x00008000
  74 #define SDRAM_CFG_BI                    0x00000001
  75
  76 #if defined(CONFIG_P4080)
  77 #define RD_TO_PRE_MASK          0xf
  78 #define RD_TO_PRE_SHIFT         13
  79 #define WR_DATA_DELAY_MASK      0xf
  80 #define WR_DATA_DELAY_SHIFT     9
  81 #else
  82 #define RD_TO_PRE_MASK          0x7
  83 #define RD_TO_PRE_SHIFT         13
  84 #define WR_DATA_DELAY_MASK      0x7
  85 #define WR_DATA_DELAY_SHIFT     10
  86 #endif
  87
  88 /* Record of register values computed */
  89 typedef struct fsl_ddr_cfg_regs_s {
  90         struct {
  91                 unsigned int bnds;
  92                 unsigned int config;
  93                 unsigned int config_2;
  94         } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
  95         unsigned int timing_cfg_3;
  96         unsigned int timing_cfg_0;
  97         unsigned int timing_cfg_1;
  98         unsigned int timing_cfg_2;
  99         unsigned int ddr_sdram_cfg;
 100         unsigned int ddr_sdram_cfg_2;
 101         unsigned int ddr_sdram_mode;
 102         unsigned int ddr_sdram_mode_2;
 103         unsigned int ddr_sdram_md_cntl;
 104         unsigned int ddr_sdram_interval;
 105         unsigned int ddr_data_init;
 106         unsigned int ddr_sdram_clk_cntl;
 107         unsigned int ddr_init_addr;
 108         unsigned int ddr_init_ext_addr;
 109         unsigned int timing_cfg_4;
 110         unsigned int timing_cfg_5;
 111         unsigned int ddr_zq_cntl;
 112         unsigned int ddr_wrlvl_cntl;
 113         unsigned int ddr_sr_cntr;
 114         unsigned int ddr_sdram_rcw_1;
 115         unsigned int ddr_sdram_rcw_2;
 116 } fsl_ddr_cfg_regs_t;
 117
 118 typedef struct memctl_options_partial_s {
 119         unsigned int all_DIMMs_ECC_capable;
 120         unsigned int all_DIMMs_tCKmax_ps;
 121         unsigned int all_DIMMs_burst_lengths_bitmask;
 122         unsigned int all_DIMMs_registered;
 123         unsigned int all_DIMMs_unbuffered;
 124         /*      unsigned int lowest_common_SPD_caslat; */
 125         unsigned int all_DIMMs_minimum_tRCD_ps;
 126 } memctl_options_partial_t;
 127
 128 /*
 129  * Generalized parameters for memory controller configuration,
 130  * might be a little specific to the FSL memory controller
 131  */
 132 typedef struct memctl_options_s {
 133         /*
 134          * Memory organization parameters
 135          *
 136          * if DIMM is present in the system
 137          * where DIMMs are with respect to chip select
 138          * where chip selects are with respect to memory boundaries
 139          */
 140         unsigned int registered_dimm_en;    /* use registered DIMM support */
 141
 142         /* Options local to a Chip Select */
 143         struct cs_local_opts_s {
 144                 unsigned int auto_precharge;
 145                 unsigned int odt_rd_cfg;
 146                 unsigned int odt_wr_cfg;
 147         } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
 148
 149         /* Special configurations for chip select */
 150         unsigned int memctl_interleaving;
 151         unsigned int memctl_interleaving_mode;
 152         unsigned int ba_intlv_ctl;
 153
 154         /* Operational mode parameters */
 155         unsigned int ECC_mode;   /* Use ECC? */
 156         /* Initialize ECC using memory controller? */
 157         unsigned int ECC_init_using_memctl;
 158         unsigned int DQS_config;        /* Use DQS? maybe only with DDR2? */
 159         /* SREN - self-refresh during sleep */
 160         unsigned int self_refresh_in_sleep;
 161         unsigned int dynamic_power;     /* DYN_PWR */
 162         /* memory data width to use (16-bit, 32-bit, 64-bit) */
 163         unsigned int data_bus_width;
 164         unsigned int burst_length;      /* BL4, OTF and BL8 */
 165         /* On-The-Fly Burst Chop enable */
 166         unsigned int OTF_burst_chop_en;
 167         /* mirrior DIMMs for DDR3 */
 168         unsigned int mirrored_dimm;
 169
 170         /* Global Timing Parameters */
 171         unsigned int cas_latency_override;
 172         unsigned int cas_latency_override_value;
 173         unsigned int use_derated_caslat;
 174         unsigned int additive_latency_override;
 175         unsigned int additive_latency_override_value;
 176
 177         unsigned int clk_adjust;                /* */
 178         unsigned int cpo_override;
 179         unsigned int write_data_delay;          /* DQS adjust */
 180
 181         unsigned int wrlvl_override;
 182         unsigned int wrlvl_sample;              /* Write leveling */
 183         unsigned int wrlvl_start;
 184
 185         unsigned int half_strength_driver_enable;
 186         unsigned int twoT_en;
 187         unsigned int threeT_en;
 188         unsigned int bstopre;
 189         unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
 190         unsigned int tFAW_window_four_activates_ps;     /* tFAW --  FOUR_ACT */
 191
 192         /* Rtt impedance */
 193         unsigned int rtt_override;              /* rtt_override enable */
 194         unsigned int rtt_override_value;        /* that is Rtt_Nom for DDR3 */
 195         unsigned int rtt_wr_override_value;     /* this is Rtt_WR for DDR3 */
 196
 197         /* Automatic self refresh */
 198         unsigned int auto_self_refresh_en;
 199         unsigned int sr_it;
 200         /* ZQ calibration */
 201         unsigned int zq_en;
 202         /* Write leveling */
 203         unsigned int wrlvl_en;
 204 } memctl_options_t;
 205
 206 extern phys_size_t fsl_ddr_sdram(void);
 207 #endif