1 /*
2 * MPC86xx Internal Memory Map
3 *
4 * Copyright 2004 Freescale Semiconductor
5 * Jeff Brown (Jeffrey@freescale.com)
6 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
7 *
8 */
10 #ifndef __IMMAP_86xx__
11 #define __IMMAP_86xx__
13 #include <asm/types.h>
14 #include <asm/fsl_dma.h>
15 #include <asm/fsl_i2c.h>
17 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
18 typedef struct ccsr_local_mcm {
19 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
20 char res1[4];
21 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
22 char res2[4];
23 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
24 char res3[12];
25 uint bptr; /* 0x20 - Boot Page Translation Register */
26 char res4[3044];
27 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
28 char res5[4];
29 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
30 char res6[20];
31 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
32 char res7[4];
33 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
34 char res8[20];
35 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
36 char res9[4];
37 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
38 char res10[20];
39 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
40 char res11[4];
41 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
42 char res12[20];
43 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
44 char res13[4];
45 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
46 char res14[20];
47 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
48 char res15[4];
49 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
50 char res16[20];
51 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
52 char res17[4];
53 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
54 char res18[20];
55 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
56 char res19[4];
57 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
58 char res20[20];
59 uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
60 char res21[4];
61 uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
62 char res22[20];
63 uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
64 char res23[4];
65 uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
66 char res24[716];
67 uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
68 char res25[4];
69 uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
70 char res26[4];
71 uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
72 char res27[44];
73 uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
74 uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
75 uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
76 uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
77 char res28[16];
78 uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
79 uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
80 uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
81 char res29[3476];
82 uint edr; /* 0x1e00 - MCM Error Detect Register */
83 char res30[4];
84 uint eer; /* 0x1e08 - MCM Error Enable Register */
85 uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
86 uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
87 uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
88 char res31[488];
89 } ccsr_local_mcm_t;
91 /* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
93 typedef struct ccsr_ddr {
94 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
95 char res1[4];
96 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
97 char res2[4];
98 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
99 char res3[4];
100 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
101 char res4[4];
102 uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
103 char res5[4];
104 uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
105 char res6[84];
106 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
107 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
108 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
109 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
110 uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
111 uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
112 char res7[104];
113 uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
114 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
115 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
116 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
117 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
118 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
119 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
120 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
121 uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
122 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
123 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
124 char res8[4];
125 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
126 char res9[12];
127 uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
128 uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
129 uint init_addr; /* 0x2148 - DDR training initialzation address */
130 uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */
131 char res10[2728];
132 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
133 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
134 char res11[512];
135 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
136 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
137 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
138 char res12[20];
139 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
140 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
141 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
142 char res13[20];
143 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
144 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
145 uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
146 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
147 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
148 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
149 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
150 char res14[164];
151 uint debug_1; /* 0x2f00 */
152 uint debug_2;
153 uint debug_3;
154 uint debug_4;
155 uint debug_5;
156 char res15[236];
157 } ccsr_ddr_t;
160 /* Daul I2C Registers(0x3000-0x4000) */
161 typedef struct ccsr_i2c {
162 struct fsl_i2c i2c[2];
163 u8 res[4096 - 2 * sizeof(struct fsl_i2c)];
164 } ccsr_i2c_t;
166 /* DUART Registers(0x4000-0x5000) */
167 typedef struct ccsr_duart {
168 char res1[1280];
169 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
170 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
171 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
172 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
173 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
174 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
175 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
176 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
177 char res2[8];
178 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
179 char res3[239];
180 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
181 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
182 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
183 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
184 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
185 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
186 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
187 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
188 char res4[8];
189 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
190 char res5[2543];
191 } ccsr_duart_t;
194 /* Local Bus Controller Registers(0x5000-0x6000) */
195 typedef struct ccsr_lbc {
196 uint br0; /* 0x5000 - LBC Base Register 0 */
197 uint or0; /* 0x5004 - LBC Options Register 0 */
198 uint br1; /* 0x5008 - LBC Base Register 1 */
199 uint or1; /* 0x500c - LBC Options Register 1 */
200 uint br2; /* 0x5010 - LBC Base Register 2 */
201 uint or2; /* 0x5014 - LBC Options Register 2 */
202 uint br3; /* 0x5018 - LBC Base Register 3 */
203 uint or3; /* 0x501c - LBC Options Register 3 */
204 uint br4; /* 0x5020 - LBC Base Register 4 */
205 uint or4; /* 0x5024 - LBC Options Register 4 */
206 uint br5; /* 0x5028 - LBC Base Register 5 */
207 uint or5; /* 0x502c - LBC Options Register 5 */
208 uint br6; /* 0x5030 - LBC Base Register 6 */
209 uint or6; /* 0x5034 - LBC Options Register 6 */
210 uint br7; /* 0x5038 - LBC Base Register 7 */
211 uint or7; /* 0x503c - LBC Options Register 7 */
212 char res1[40];
213 uint mar; /* 0x5068 - LBC UPM Address Register */
214 char res2[4];
215 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
216 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
217 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
218 char res3[8];
219 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
220 uint mdr; /* 0x5088 - LBC UPM Data Register */
221 char res4[8];
222 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
223 char res5[8];
224 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
225 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
226 char res6[8];
227 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
228 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
229 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
230 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
231 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
232 char res7[12];
233 uint lbcr; /* 0x50d0 - LBC Configuration Register */
234 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
235 char res8[3880];
236 } ccsr_lbc_t;
238 /* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
239 typedef struct ccsr_pex {
240 uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
241 uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
242 char res1[4];
243 uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
244 char res2[16];
245 uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
246 uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
247 uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
248 uint pm_command; /* 0x802c - PEX PM Command register */
249 char res3[3016];
250 uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
251 uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
252 uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
253 uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
254 char res4[8];
255 uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
256 char res5[12];
257 uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
258 uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
259 uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
260 char res6[4];
261 uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
262 char res7[12];
263 uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
264 uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
265 uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
266 char res8[4];
267 uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
268 char res9[12];
269 uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
270 uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
271 uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
272 char res10[4];
273 uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
274 char res11[12];
275 uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
276 uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
277 uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
278 char res12[4];
279 uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
280 char res13[12];
281 char res14[256];
282 uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
283 char res15[4];
284 uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
285 uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
286 uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
287 char res16[12];
288 uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
289 char res17[4];
290 uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
291 uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
292 uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
293 char res18[12];
294 uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
295 char res19[4];
296 uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
297 uint piwbear1;
298 uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
299 char res20[12];
300 uint pedr; /* 0x8e00 - PEX Error Detect Register */
301 char res21[4];
302 uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */
303 char res22[4];
304 uint pecdr; /* 0x8e10 - PEX Error Disable Register */
305 char res23[12];
306 uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */
307 char res24[4];
308 uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */
309 uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */
310 uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */
311 uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */
312 char res25[452];
313 char res26[4];
314 } ccsr_pex_t;
316 /* Hyper Transport Register Block (0xA000-0xB000) */
317 typedef struct ccsr_ht {
318 uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
319 uint hcfg_data; /* 0xa004 - HT Configuration Data register */
320 char res1[3064];
321 uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
322 char res2[12];
323 uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
324 char res3[12];
325 uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
326 char res4[4];
327 uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
328 char res5[4];
329 uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
330 char res6[12];
331 uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
332 char res7[4];
333 uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
334 char res8[4];
335 uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
336 char res9[12];
337 uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
338 char res10[4];
339 uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
340 char res11[4];
341 uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
342 char res12[12];
343 uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
344 char res13[4];
345 uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
346 char res14[4];
347 uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
348 char res15[236];
349 uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
350 char res16[4];
351 uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
352 char res17[4];
353 uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
354 char res18[12];
355 uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
356 char res19[4];
357 uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
358 char res20[4];
359 uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
360 char res21[12];
361 uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
362 char res22[4];
363 uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
364 char res23[4];
365 uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
366 char res24[12];
367 uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
368 char res25[4];
369 uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
370 char res26[4];
371 uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
372 char res27[12];
373 uint hedr; /* 0xae00 - HT Error Detect register */
374 char res28[4];
375 uint heier; /* 0xae08 - HT Error Interrupt Enable register */
376 char res29[4];
377 uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
378 char res30[12];
379 uint hecsr; /* 0xae20 - HT Error Capture Status register */
380 char res31[4];
381 uint hec0; /* 0xae28 - HT Error Capture 0 register */
382 uint hec1; /* 0xae2c - HT Error Capture 1 register */
383 uint hec2; /* 0xae30 - HT Error Capture 2 register */
384 char res32[460];
385 } ccsr_ht_t;
387 /* DMA Registers(0x2_1000-0x2_2000) */
388 typedef struct ccsr_dma {
389 char res1[256];
390 struct fsl_dma dma[4];
391 uint dgsr; /* 0x21300 - DMA General Status Register */
392 char res2[3324];
393 } ccsr_dma_t;
395 /* tsec1-4: 24000-28000 */
396 typedef struct ccsr_tsec {
397 uint id; /* 0x24000 - Controller ID Register */
398 char res1[12];
399 uint ievent; /* 0x24010 - Interrupt Event Register */
400 uint imask; /* 0x24014 - Interrupt Mask Register */
401 uint edis; /* 0x24018 - Error Disabled Register */
402 char res2[4];
403 uint ecntrl; /* 0x24020 - Ethernet Control Register */
404 char res2_1[4];
405 uint ptv; /* 0x24028 - Pause Time Value Register */
406 uint dmactrl; /* 0x2402c - DMA Control Register */
407 uint tbipa; /* 0x24030 - TBI PHY Address Register */
408 char res3[88];
409 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
410 char res4[8];
411 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
412 uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
413 char res4_1[4];
414 uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
415 uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
416 char res5[84];
417 uint tctrl; /* 0x24100 - Transmit Control Register */
418 uint tstat; /* 0x24104 - Transmit Status Register */
419 uint dfvlan; /* 0x24108 - Default VLAN control word */
420 char res6[4];
421 uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
422 uint tqueue; /* 0x24114 - Transmit Queue Control Register */
423 char res7[40];
424 uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
425 uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
426 char res8[52];
427 uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
428 char res9[4];
429 uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
430 char res10[4];
431 uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
432 char res11[4];
433 uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
434 char res12[4];
435 uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
436 char res13[4];
437 uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
438 char res14[4];
439 uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
440 char res15[4];
441 uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
442 char res16[4];
443 uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
444 char res17[64];
445 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
446 uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
447 char res18[4];
448 uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
449 char res19[4];
450 uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
451 char res20[4];
452 uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
453 char res21[4];
454 uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
455 char res22[4];
456 uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
457 char res23[4];
458 uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
459 char res24[4];
460 uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
461 char res25[192];
462 uint rctrl; /* 0x24300 - Receive Control Register */
463 uint rstat; /* 0x24304 - Receive Status Register */
464 char res26[8];
465 uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
466 uint rqueue; /* 0x24314 - Receive queue control register */
467 char res27[24];
468 uint rbifx; /* 0x24330 - Receive bit field extract control Register */
469 uint rqfar; /* 0x24334 - Receive queue filing table address Register */
470 uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
471 uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
472 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
473 char res28[56];
474 uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
475 char res29[4];
476 uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
477 char res30[4];
478 uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
479 char res31[4];
480 uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
481 char res32[4];
482 uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
483 char res33[4];
484 uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
485 char res34[4];
486 uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
487 char res35[4];
488 uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
489 char res36[4];
490 uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
491 char res37[64];
492 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
493 uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
494 char res38[4];
495 uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
496 char res39[4];
497 uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
498 char res40[4];
499 uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
500 char res41[4];
501 uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
502 char res42[4];
503 uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
504 char res43[4];
505 uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
506 char res44[4];
507 uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
508 char res45[192];
509 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
510 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
511 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
512 uint hafdup; /* 0x2450c - Half Duplex Register */
513 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
514 char res46[12];
515 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
516 uint miimcom; /* 0x24524 - MII Management Command Register */
517 uint miimadd; /* 0x24528 - MII Management Address Register */
518 uint miimcon; /* 0x2452c - MII Management Control Register */
519 uint miimstat; /* 0x24530 - MII Management Status Register */
520 uint miimind; /* 0x24534 - MII Management Indicator Register */
521 uint ifctrl; /* 0x24538 - Interface Contrl Register */
522 uint ifstat; /* 0x2453c - Interface Status Register */
523 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
524 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
525 uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
526 uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
527 uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
528 uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
529 uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
530 uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
531 uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
532 uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
533 uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
534 uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
535 uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
536 uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
537 uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
538 uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
539 uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
540 uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
541 uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
542 uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
543 uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
544 uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
545 uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
546 uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
547 uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
548 uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
549 uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
550 uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
551 uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
552 uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
553 uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
554 uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
555 char res48[192];
556 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
557 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
558 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
559 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
560 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
561 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
562 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
563 uint rbyt; /* 0x2469c - Receive Byte Counter */
564 uint rpkt; /* 0x246a0 - Receive Packet Counter */
565 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
566 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
567 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
568 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
569 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
570 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
571 uint raln; /* 0x246bc - Receive Alignment Error Counter */
572 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
573 uint rcde; /* 0x246c4 - Receive Code Error Counter */
574 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
575 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
576 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
577 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
578 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
579 uint rdrp; /* 0x246dc - Receive Drop Counter */
580 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
581 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
582 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
583 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
584 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
585 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
586 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
587 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
588 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
589 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
590 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
591 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
592 char res49[4];
593 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
594 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
595 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
596 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
597 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
598 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
599 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
600 uint car1; /* 0x24730 - Carry Register One */
601 uint car2; /* 0x24734 - Carry Register Two */
602 uint cam1; /* 0x24738 - Carry Mask Register One */
603 uint cam2; /* 0x2473c - Carry Mask Register Two */
604 uint rrej; /* 0x24740 - Receive filer rejected packet counter */
605 char res50[188];
606 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
607 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
608 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
609 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
610 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
611 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
612 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
613 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
614 char res51[96];
615 uint gaddr0; /* 0x24880 - Global address register 0 */
616 uint gaddr1; /* 0x24884 - Global address register 1 */
617 uint gaddr2; /* 0x24888 - Global address register 2 */
618 uint gaddr3; /* 0x2488c - Global address register 3 */
619 uint gaddr4; /* 0x24890 - Global address register 4 */
620 uint gaddr5; /* 0x24894 - Global address register 5 */
621 uint gaddr6; /* 0x24898 - Global address register 6 */
622 uint gaddr7; /* 0x2489c - Global address register 7 */
623 char res52[352];
624 uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
625 char res53[500];
626 uint attr; /* 0x24BF8 - DMA Attribute register */
627 uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
628 char res54[1024];
629 } ccsr_tsec_t;
631 /* PIC Registers(0x4_0000-0x6_1000) */
633 typedef struct ccsr_pic {
634 char res1[64];
635 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
636 char res2[12];
637 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
638 char res3[12];
639 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
640 char res4[12];
641 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
642 char res5[12];
643 uint ctpr; /* 0x40080 - Current Task Priority Register */
644 char res6[12];
645 uint whoami; /* 0x40090 - Who Am I Register */
646 char res7[12];
647 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
648 char res8[12];
649 uint eoi; /* 0x400b0 - End Of Interrupt Register */
650 char res9[3916];
651 uint frr; /* 0x41000 - Feature Reporting Register */
652 char res10[28];
653 uint gcr; /* 0x41020 - Global Configuration Register */
654 #define MPC86xx_PICGCR_RST 0x80000000
655 #define MPC86xx_PICGCR_MODE 0x20000000
656 char res11[92];
657 uint vir; /* 0x41080 - Vendor Identification Register */
658 char res12[12];
659 uint pir; /* 0x41090 - Processor Initialization Register */
660 char res13[12];
661 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
662 char res14[12];
663 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
664 char res15[12];
665 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
666 char res16[12];
667 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
668 char res17[12];
669 uint svr; /* 0x410e0 - Spurious Vector Register */
670 char res18[12];
671 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
672 char res19[12];
673 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
674 char res20[12];
675 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
676 char res21[12];
677 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
678 char res22[12];
679 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
680 char res23[12];
681 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
682 char res24[12];
683 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
684 char res25[12];
685 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
686 char res26[12];
687 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
688 char res27[12];
689 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
690 char res28[12];
691 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
692 char res29[12];
693 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
694 char res30[12];
695 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
696 char res31[12];
697 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
698 char res32[12];
699 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
700 char res33[12];
701 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
702 char res34[12];
703 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
704 char res35[268];
705 uint tcr; /* 0x41300 - Timer Control Register */
706 char res36[12];
707 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
708 char res37[12];
709 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
710 char res38[12];
711 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
712 char res39[12];
713 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
714 char res40[12];
715 uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
716 char res41[12];
717 uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
718 char res42[12];
719 uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
720 char res43[12];
721 uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
722 char res44[12];
723 uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
724 char res45[12];
725 uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
726 char res46[12];
727 uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
728 char res47[12];
729 uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
730 char res48[60];
731 uint msgr0; /* 0x41400 - Message Register 0 */
732 char res49[12];
733 uint msgr1; /* 0x41410 - Message Register 1 */
734 char res50[12];
735 uint msgr2; /* 0x41420 - Message Register 2 */
736 char res51[12];
737 uint msgr3; /* 0x41430 - Message Register 3 */
738 char res52[204];
739 uint mer; /* 0x41500 - Message Enable Register */
740 char res53[12];
741 uint msr; /* 0x41510 - Message Status Register */
742 char res54[60140];
743 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
744 char res55[12];
745 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
746 char res56[12];
747 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
748 char res57[12];
749 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
750 char res58[12];
751 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
752 char res59[12];
753 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
754 char res60[12];
755 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
756 char res61[12];
757 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
758 char res62[12];
759 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
760 char res63[12];
761 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
762 char res64[12];
763 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
764 char res65[12];
765 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
766 char res66[12];
767 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
768 char res67[12];
769 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
770 char res68[12];
771 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
772 char res69[12];
773 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
774 char res70[12];
775 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
776 char res71[12];
777 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
778 char res72[12];
779 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
780 char res73[12];
781 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
782 char res74[12];
783 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
784 char res75[12];
785 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
786 char res76[12];
787 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
788 char res77[12];
789 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
790 char res78[140];
791 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
792 char res79[12];
793 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
794 char res80[12];
795 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
796 char res81[12];
797 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
798 char res82[12];
799 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
800 char res83[12];
801 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
802 char res84[12];
803 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
804 char res85[12];
805 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
806 char res86[12];
807 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
808 char res87[12];
809 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
810 char res88[12];
811 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
812 char res89[12];
813 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
814 char res90[12];
815 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
816 char res91[12];
817 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
818 char res92[12];
819 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
820 char res93[12];
821 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
822 char res94[12];
823 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
824 char res95[12];
825 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
826 char res96[12];
827 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
828 char res97[12];
829 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
830 char res98[12];
831 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
832 char res99[12];
833 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
834 char res100[12];
835 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
836 char res101[12];
837 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
838 char res102[12];
839 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
840 char res103[12];
841 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
842 char res104[12];
843 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
844 char res105[12];
845 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
846 char res106[12];
847 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
848 char res107[12];
849 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
850 char res108[12];
851 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
852 char res109[12];
853 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
854 char res110[12];
855 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
856 char res111[12];
857 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
858 char res112[12];
859 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
860 char res113[12];
861 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
862 char res114[12];
863 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
864 char res115[12];
865 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
866 char res116[12];
867 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
868 char res117[12];
869 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
870 char res118[12];
871 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
872 char res119[12];
873 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
874 char res120[12];
875 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
876 char res121[12];
877 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
878 char res122[12];
879 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
880 char res123[12];
881 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
882 char res124[12];
883 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
884 char res125[12];
885 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
886 char res126[12];
887 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
888 char res127[12];
889 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
890 char res128[12];
891 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
892 char res129[12];
893 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
894 char res130[12];
895 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
896 char res131[12];
897 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
898 char res132[12];
899 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
900 char res133[12];
901 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
902 char res134[12];
903 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
904 char res135[12];
905 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
906 char res136[12];
907 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
908 char res137[12];
909 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
910 char res138[12];
911 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
912 char res139[12];
913 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
914 char res140[12];
915 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
916 char res141[12];
917 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
918 char res142[4108];
919 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
920 char res143[12];
921 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
922 char res144[12];
923 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
924 char res145[12];
925 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
926 char res146[12];
927 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
928 char res147[12];
929 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
930 char res148[12];
931 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
932 char res149[12];
933 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
934 char res150[59852];
935 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
936 char res151[12];
937 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
938 char res152[12];
939 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
940 char res153[12];
941 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
942 char res154[12];
943 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
944 char res155[12];
945 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
946 char res156[12];
947 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
948 char res157[12];
949 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
950 char res158[3916];
951 } ccsr_pic_t;
953 /* RapidIO Registers(0xc_0000-0xe_0000) */
955 typedef struct ccsr_rio {
956 uint didcar; /* 0xc0000 - Device Identity Capability Register */
957 uint dicar; /* 0xc0004 - Device Information Capability Register */
958 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
959 uint aicar; /* 0xc000c - Assembly Information Capability Register */
960 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
961 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
962 uint socar; /* 0xc0018 - Source Operations Capability Register */
963 uint docar; /* 0xc001c - Destination Operations Capability Register */
964 char res1[32];
965 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
966 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
967 char res2[4];
968 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
969 char res3[12];
970 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
971 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
972 char res4[4];
973 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
974 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
975 char res5[144];
976 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
977 char res6[28];
978 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
979 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
980 char res7[20];
981 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
982 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
983 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
984 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
985 char res8[12];
986 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
987 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
988 char res9[1184];
989 uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
990 char res10[4];
991 uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
992 uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
993 char res11[4];
994 uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
995 uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
996 uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
997 char res12[32];
998 uint edcsr; /* 0xc0640 - Port 0 error detect status register */
999 uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
1000 uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
1001 uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
1002 uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
1003 uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
1004 uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
1005 char res13[12];
1006 uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
1007 uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
1008 char res14[63892];
1009 uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
1010 char res15[12];
1011 uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
1012 char res16[12];
1013 uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
1014 char res17[92];
1015 uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
1016 char res18[124];
1017 uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
1018 char res19[28];
1019 uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
1020 char res20[12];
1021 uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
1022 char res21[12];
1023 uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
1024 char res22[20];
1025 uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
1026 char res23[4];
1027 uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
1028 char res24[2716];
1029 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1030 uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
1031 char res25[8];
1032 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1033 char res26[12];
1034 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1035 uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
1036 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1037 char res27[4];
1038 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1039 uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
1040 uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
1041 uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
1042 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1043 uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
1044 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1045 char res28[4];
1046 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1047 uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
1048 uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
1049 uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
1050 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1051 uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
1052 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1053 char res29[4];
1054 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1055 uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
1056 uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
1057 uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
1058 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1059 uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
1060 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1061 char res30[4];
1062 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1063 uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
1064 uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
1065 uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
1066 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1067 uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
1068 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1069 char res31[4];
1070 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1071 uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
1072 uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
1073 uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
1074 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1075 uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
1076 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1077 char res32[4];
1078 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1079 uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
1080 uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
1081 uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
1082 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1083 uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
1084 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1085 char res33[4];
1086 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1087 uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
1088 uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
1089 uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
1090 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1091 uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
1092 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1093 char res34[4];
1094 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1095 uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
1096 uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
1097 uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
1098 char res35[64];
1099 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1100 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1101 char res36[4];
1102 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1103 char res37[12];
1104 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1105 char res38[4];
1106 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1107 char res39[4];
1108 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1109 char res40[12];
1110 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1111 char res41[4];
1112 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1113 char res42[4];
1114 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1115 char res43[12];
1116 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1117 char res44[4];
1118 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1119 char res45[4];
1120 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1121 char res46[12];
1122 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1123 char res47[12];
1124 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1125 char res48[12];
1126 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1127 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1128 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1129 uint pecr; /* 0xd0e0c - Port Error Control Register */
1130 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1131 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1132 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1133 char res49[4];
1134 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1135 char res50[4];
1136 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1137 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1138 char res51[8656];
1139 uint omr; /* 0xd3000 - Outbound Mode Register */
1140 uint osr; /* 0xd3004 - Outbound Status Register */
1141 uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1142 uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
1143 uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
1144 uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
1145 uint odpr; /* 0xd3018 - Outbound Destination Port Register */
1146 uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
1147 uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
1148 uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1149 uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
1150 uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
1151 uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
1152 uint omlr; /* 0xd3034 - Outbound Multicast List Register */
1153 char res52[40];
1154 uint imr; /* 0xd3060 - Outbound Mode Register */
1155 uint isr; /* 0xd3064 - Inbound Status Register */
1156 uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1157 uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
1158 uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
1159 uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
1160 uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
1161 char res53[900];
1162 uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
1163 uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
1164 char res54[16];
1165 uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
1166 uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
1167 char res55[12];
1168 uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
1169 char res56[48];
1170 uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
1171 uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
1172 uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
1173 uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
1174 uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
1175 uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
1176 uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
1177 char res57[100];
1178 uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
1179 uint pwsr; /* 0xd34e4 - Port-Write Status Register */
1180 uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
1181 uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
1182 char res58[51984];
1183 } ccsr_rio_t;
1185 /* Global Utilities Register Block(0xe_0000-0xf_ffff) */
1186 typedef struct ccsr_gur {
1187 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1188 uint porbmsr; /* 0xe0004 - POR boot mode status register */
1189 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1190 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
1191 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
1192 char res1[12];
1193 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1194 char res2[12];
1195 uint gpiocr; /* 0xe0030 - GPIO control register */
1196 char res3[12];
1197 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1198 char res4[12];
1199 uint gpindr; /* 0xe0050 - General-purpose input data register */
1200 char res5[12];
1201 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1202 char res6[12];
1203 uint devdisr; /* 0xe0070 - Device disable control */
1204 char res7[12];
1205 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1206 char res8[12];
1207 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1208 uint rstrscr; /* 0xe0094 - Reset request status and control register */
1209 char res9[8];
1210 uint pvr; /* 0xe00a0 - Processor version register */
1211 uint svr; /* 0xe00a4 - System version register */
1212 char res10a[8];
1213 uint rstcr; /* 0xe00b0 - Reset control register */
1214 char res10b[1868];
1215 uint clkdvdr; /* 0xe0800 - Clock Divide register */
1216 char res10c[796];
1217 uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */
1218 char res10d[4];
1219 uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */
1220 char res10e[724];
1221 uint clkocr; /* 0xe0e00 - Clock out select register */
1222 char res11[12];
1223 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1224 char res12[12];
1225 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
1226 char res13a[224];
1227 uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */
1228 char res13b[4];
1229 uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */
1230 char res14[24];
1231 uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
1232 char res15a[24];
1233 uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */
1234 uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */
1235 char res16[184];
1236 } ccsr_gur_t;
1238 #define MPC8610_PORBMSR_HA 0x00070000
1239 #define MPC8610_PORBMSR_HA_SHIFT 16
1240 #define MPC8641_PORBMSR_HA 0x00060000
1241 #define MPC8641_PORBMSR_HA_SHIFT 17
1242 #define MPC8610_PORDEVSR_IO_SEL 0x00380000
1243 #define MPC8610_PORDEVSR_IO_SEL_SHIFT 19
1244 #define MPC8641_PORDEVSR_IO_SEL 0x000F0000
1245 #define MPC8641_PORDEVSR_IO_SEL_SHIFT 16
1246 #define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
1247 #define MPC86xx_DEVDISR_PCIEX1 0x80000000
1248 #define MPC86xx_DEVDISR_PCIEX2 0x40000000
1249 #define MPC86xx_DEVDISR_PCI1 0x80000000
1250 #define MPC86xx_DEVDISR_PCIE1 0x40000000
1251 #define MPC86xx_DEVDISR_PCIE2 0x20000000
1252 #define MPC86xx_DEVDISR_CPU0 0x00008000
1253 #define MPC86xx_DEVDISR_CPU1 0x00004000
1254 #define MPC86xx_RSTCR_HRST_REQ 0x00000002
1256 /*
1257 * Watchdog register block(0xe_4000-0xe_4fff)
1258 */
1259 typedef struct ccsr_wdt {
1260 uint res0;
1261 uint swcrr; /* System watchdog control register */
1262 uint swcnr; /* System watchdog count register */
1263 char res1[2];
1264 ushort swsrr; /* System watchdog service register */
1265 char res2[4080];
1266 } ccsr_wdt_t;
1268 typedef struct immap {
1269 ccsr_local_mcm_t im_local_mcm;
1270 ccsr_ddr_t im_ddr1;
1271 ccsr_i2c_t im_i2c;
1272 ccsr_duart_t im_duart;
1273 ccsr_lbc_t im_lbc;
1274 ccsr_ddr_t im_ddr2;
1275 char res1[4096];
1276 ccsr_pex_t im_pex1;
1277 ccsr_pex_t im_pex2;
1278 ccsr_ht_t im_ht;
1279 char res2[90112];
1280 ccsr_dma_t im_dma;
1281 char res3[8192];
1282 ccsr_tsec_t im_tsec1;
1283 ccsr_tsec_t im_tsec2;
1284 ccsr_tsec_t im_tsec3;
1285 ccsr_tsec_t im_tsec4;
1286 char res4[98304];
1287 ccsr_pic_t im_pic;
1288 char res5[389120];
1289 ccsr_rio_t im_rio;
1290 ccsr_gur_t im_gur;
1291 char res6[12288];
1292 ccsr_wdt_t im_wdt;
1293 } immap_t;
1295 extern immap_t *immr;
1297 #define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000)
1298 #define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
1299 #define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000)
1300 #define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
1301 #define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
1302 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
1304 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
1305 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
1307 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
1308 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
1310 #endif /*__IMMAP_86xx__*/