1 /*
2 * QUICC Engine (QE) Internal Memory Map.
3 * The Internal Memory Map for devices with QE on them. This
4 * is the superset of all QE devices (8360, etc.).
5 *
6 * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
7 * Author: Shlomi Gridih <gridish@freescale.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
15 #ifndef __IMMAP_QE_H__
16 #define __IMMAP_QE_H__
18 #ifdef CONFIG_MPC83xx
19 #if defined(CONFIG_MPC8360)
20 #define QE_MURAM_SIZE 0xc000UL
21 #define MAX_QE_RISC 2
22 #define QE_NUM_OF_SNUM 28
23 #elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
24 #define QE_MURAM_SIZE 0x4000UL
25 #define MAX_QE_RISC 1
26 #define QE_NUM_OF_SNUM 28
27 #endif
28 #endif
30 /* QE I-RAM */
31 typedef struct qe_iram {
32 u32 iadd; /* I-RAM Address Register */
33 u32 idata; /* I-RAM Data Register */
34 u8 res0[0x4];
35 u32 iready;
36 u8 res1[0x70];
37 } __attribute__ ((packed)) qe_iram_t;
39 /* QE Interrupt Controller */
40 typedef struct qe_ic {
41 u32 qicr;
42 u32 qivec;
43 u32 qripnr;
44 u32 qipnr;
45 u32 qipxcc;
46 u32 qipycc;
47 u32 qipwcc;
48 u32 qipzcc;
49 u32 qimr;
50 u32 qrimr;
51 u32 qicnr;
52 u8 res0[0x4];
53 u32 qiprta;
54 u32 qiprtb;
55 u8 res1[0x4];
56 u32 qricr;
57 u8 res2[0x20];
58 u32 qhivec;
59 u8 res3[0x1C];
60 } __attribute__ ((packed)) qe_ic_t;
62 /* Communications Processor */
63 typedef struct cp_qe {
64 u32 cecr; /* QE command register */
65 u32 ceccr; /* QE controller configuration register */
66 u32 cecdr; /* QE command data register */
67 u8 res0[0xA];
68 u16 ceter; /* QE timer event register */
69 u8 res1[0x2];
70 u16 cetmr; /* QE timers mask register */
71 u32 cetscr; /* QE time-stamp timer control register */
72 u32 cetsr1; /* QE time-stamp register 1 */
73 u32 cetsr2; /* QE time-stamp register 2 */
74 u8 res2[0x8];
75 u32 cevter; /* QE virtual tasks event register */
76 u32 cevtmr; /* QE virtual tasks mask register */
77 u16 cercr; /* QE RAM control register */
78 u8 res3[0x2];
79 u8 res4[0x24];
80 u16 ceexe1; /* QE external request 1 event register */
81 u8 res5[0x2];
82 u16 ceexm1; /* QE external request 1 mask register */
83 u8 res6[0x2];
84 u16 ceexe2; /* QE external request 2 event register */
85 u8 res7[0x2];
86 u16 ceexm2; /* QE external request 2 mask register */
87 u8 res8[0x2];
88 u16 ceexe3; /* QE external request 3 event register */
89 u8 res9[0x2];
90 u16 ceexm3; /* QE external request 3 mask register */
91 u8 res10[0x2];
92 u16 ceexe4; /* QE external request 4 event register */
93 u8 res11[0x2];
94 u16 ceexm4; /* QE external request 4 mask register */
95 u8 res12[0x2];
96 u8 res13[0x280];
97 } __attribute__ ((packed)) cp_qe_t;
99 /* QE Multiplexer */
100 typedef struct qe_mux {
101 u32 cmxgcr; /* CMX general clock route register */
102 u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
103 u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
104 u32 cmxsi1syr; /* CMX SI1 SYNC route register */
105 u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
106 u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
107 u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
108 u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
109 u32 cmxupcr; /* CMX UPC clock route register */
110 u8 res0[0x1C];
111 } __attribute__ ((packed)) qe_mux_t;
113 /* QE Timers */
114 typedef struct qe_timers {
115 u8 gtcfr1; /* Timer 1 2 global configuration register */
116 u8 res0[0x3];
117 u8 gtcfr2; /* Timer 3 4 global configuration register */
118 u8 res1[0xB];
119 u16 gtmdr1; /* Timer 1 mode register */
120 u16 gtmdr2; /* Timer 2 mode register */
121 u16 gtrfr1; /* Timer 1 reference register */
122 u16 gtrfr2; /* Timer 2 reference register */
123 u16 gtcpr1; /* Timer 1 capture register */
124 u16 gtcpr2; /* Timer 2 capture register */
125 u16 gtcnr1; /* Timer 1 counter */
126 u16 gtcnr2; /* Timer 2 counter */
127 u16 gtmdr3; /* Timer 3 mode register */
128 u16 gtmdr4; /* Timer 4 mode register */
129 u16 gtrfr3; /* Timer 3 reference register */
130 u16 gtrfr4; /* Timer 4 reference register */
131 u16 gtcpr3; /* Timer 3 capture register */
132 u16 gtcpr4; /* Timer 4 capture register */
133 u16 gtcnr3; /* Timer 3 counter */
134 u16 gtcnr4; /* Timer 4 counter */
135 u16 gtevr1; /* Timer 1 event register */
136 u16 gtevr2; /* Timer 2 event register */
137 u16 gtevr3; /* Timer 3 event register */
138 u16 gtevr4; /* Timer 4 event register */
139 u16 gtps; /* Timer 1 prescale register */
140 u8 res2[0x46];
141 } __attribute__ ((packed)) qe_timers_t;
143 /* BRG */
144 typedef struct qe_brg {
145 u32 brgc1; /* BRG1 configuration register */
146 u32 brgc2; /* BRG2 configuration register */
147 u32 brgc3; /* BRG3 configuration register */
148 u32 brgc4; /* BRG4 configuration register */
149 u32 brgc5; /* BRG5 configuration register */
150 u32 brgc6; /* BRG6 configuration register */
151 u32 brgc7; /* BRG7 configuration register */
152 u32 brgc8; /* BRG8 configuration register */
153 u32 brgc9; /* BRG9 configuration register */
154 u32 brgc10; /* BRG10 configuration register */
155 u32 brgc11; /* BRG11 configuration register */
156 u32 brgc12; /* BRG12 configuration register */
157 u32 brgc13; /* BRG13 configuration register */
158 u32 brgc14; /* BRG14 configuration register */
159 u32 brgc15; /* BRG15 configuration register */
160 u32 brgc16; /* BRG16 configuration register */
161 u8 res0[0x40];
162 } __attribute__ ((packed)) qe_brg_t;
164 /* SPI */
165 typedef struct spi {
166 u8 res0[0x20];
167 u32 spmode; /* SPI mode register */
168 u8 res1[0x2];
169 u8 spie; /* SPI event register */
170 u8 res2[0x1];
171 u8 res3[0x2];
172 u8 spim; /* SPI mask register */
173 u8 res4[0x1];
174 u8 res5[0x1];
175 u8 spcom; /* SPI command register */
176 u8 res6[0x2];
177 u32 spitd; /* SPI transmit data register (cpu mode) */
178 u32 spird; /* SPI receive data register (cpu mode) */
179 u8 res7[0x8];
180 } __attribute__ ((packed)) spi_t;
182 /* SI */
183 typedef struct si1 {
184 u16 siamr1; /* SI1 TDMA mode register */
185 u16 sibmr1; /* SI1 TDMB mode register */
186 u16 sicmr1; /* SI1 TDMC mode register */
187 u16 sidmr1; /* SI1 TDMD mode register */
188 u8 siglmr1_h; /* SI1 global mode register high */
189 u8 res0[0x1];
190 u8 sicmdr1_h; /* SI1 command register high */
191 u8 res2[0x1];
192 u8 sistr1_h; /* SI1 status register high */
193 u8 res3[0x1];
194 u16 sirsr1_h; /* SI1 RAM shadow address register high */
195 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
196 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
197 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
198 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
199 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
200 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
201 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
202 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
203 u8 res4[0x8];
204 u16 siemr1; /* SI1 TDME mode register 16 bits */
205 u16 sifmr1; /* SI1 TDMF mode register 16 bits */
206 u16 sigmr1; /* SI1 TDMG mode register 16 bits */
207 u16 sihmr1; /* SI1 TDMH mode register 16 bits */
208 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
209 u8 res5[0x1];
210 u8 sicmdr1_l; /* SI1 command register low 8 bits */
211 u8 res6[0x1];
212 u8 sistr1_l; /* SI1 status register low 8 bits */
213 u8 res7[0x1];
214 u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
215 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
216 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
217 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
218 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
219 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
220 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
221 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
222 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
223 u8 res8[0x8];
224 u32 siml1; /* SI1 multiframe limit register */
225 u8 siedm1; /* SI1 extended diagnostic mode register */
226 u8 res9[0xBB];
227 } __attribute__ ((packed)) si1_t;
229 /* SI Routing Tables */
230 typedef struct sir {
231 u8 tx[0x400];
232 u8 rx[0x400];
233 u8 res0[0x800];
234 } __attribute__ ((packed)) sir_t;
236 /* USB Controller. */
237 typedef struct usb_ctlr {
238 u8 usb_usmod;
239 u8 usb_usadr;
240 u8 usb_uscom;
241 u8 res1[1];
242 u16 usb_usep1;
243 u16 usb_usep2;
244 u16 usb_usep3;
245 u16 usb_usep4;
246 u8 res2[4];
247 u16 usb_usber;
248 u8 res3[2];
249 u16 usb_usbmr;
250 u8 res4[1];
251 u8 usb_usbs;
252 u16 usb_ussft;
253 u8 res5[2];
254 u16 usb_usfrn;
255 u8 res6[0x22];
256 } __attribute__ ((packed)) usb_t;
258 /* MCC */
259 typedef struct mcc {
260 u32 mcce; /* MCC event register */
261 u32 mccm; /* MCC mask register */
262 u32 mccf; /* MCC configuration register */
263 u32 merl; /* MCC emergency request level register */
264 u8 res0[0xF0];
265 } __attribute__ ((packed)) mcc_t;
267 /* QE UCC Slow */
268 typedef struct ucc_slow {
269 u32 gumr_l; /* UCCx general mode register (low) */
270 u32 gumr_h; /* UCCx general mode register (high) */
271 u16 upsmr; /* UCCx protocol-specific mode register */
272 u8 res0[0x2];
273 u16 utodr; /* UCCx transmit on demand register */
274 u16 udsr; /* UCCx data synchronization register */
275 u16 ucce; /* UCCx event register */
276 u8 res1[0x2];
277 u16 uccm; /* UCCx mask register */
278 u8 res2[0x1];
279 u8 uccs; /* UCCx status register */
280 u8 res3[0x24];
281 u16 utpt;
282 u8 guemr; /* UCC general extended mode register */
283 u8 res4[0x200 - 0x091];
284 } __attribute__ ((packed)) ucc_slow_t;
286 typedef struct ucc_mii_mng {
287 u32 miimcfg; /* MII management configuration reg */
288 u32 miimcom; /* MII management command reg */
289 u32 miimadd; /* MII management address reg */
290 u32 miimcon; /* MII management control reg */
291 u32 miimstat; /* MII management status reg */
292 u32 miimind; /* MII management indication reg */
293 u32 ifctl; /* interface control reg */
294 u32 ifstat; /* interface statux reg */
295 } __attribute__ ((packed))uec_mii_t;
297 typedef struct ucc_ethernet {
298 u32 maccfg1; /* mac configuration reg. 1 */
299 u32 maccfg2; /* mac configuration reg. 2 */
300 u32 ipgifg; /* interframe gap reg. */
301 u32 hafdup; /* half-duplex reg. */
302 u8 res1[0x10];
303 u32 miimcfg; /* MII management configuration reg */
304 u32 miimcom; /* MII management command reg */
305 u32 miimadd; /* MII management address reg */
306 u32 miimcon; /* MII management control reg */
307 u32 miimstat; /* MII management status reg */
308 u32 miimind; /* MII management indication reg */
309 u32 ifctl; /* interface control reg */
310 u32 ifstat; /* interface statux reg */
311 u32 macstnaddr1; /* mac station address part 1 reg */
312 u32 macstnaddr2; /* mac station address part 2 reg */
313 u8 res2[0x8];
314 u32 uempr; /* UCC Ethernet Mac parameter reg */
315 u32 utbipar; /* UCC tbi address reg */
316 u16 uescr; /* UCC Ethernet statistics control reg */
317 u8 res3[0x180 - 0x15A];
318 u32 tx64; /* Total number of frames (including bad
319 * frames) transmitted that were exactly
320 * of the minimal length (64 for un tagged,
321 * 68 for tagged, or with length exactly
322 * equal to the parameter MINLength */
323 u32 tx127; /* Total number of frames (including bad
324 * frames) transmitted that were between
325 * MINLength (Including FCS length==4)
326 * and 127 octets */
327 u32 tx255; /* Total number of frames (including bad
328 * frames) transmitted that were between
329 * 128 (Including FCS length==4) and 255
330 * octets */
331 u32 rx64; /* Total number of frames received including
332 * bad frames that were exactly of the
333 * mninimal length (64 bytes) */
334 u32 rx127; /* Total number of frames (including bad
335 * frames) received that were between
336 * MINLength (Including FCS length==4)
337 * and 127 octets */
338 u32 rx255; /* Total number of frames (including
339 * bad frames) received that were between
340 * 128 (Including FCS length==4) and 255
341 * octets */
342 u32 txok; /* Total number of octets residing in frames
343 * that where involved in succesfull
344 * transmission */
345 u16 txcf; /* Total number of PAUSE control frames
346 * transmitted by this MAC */
347 u8 res4[0x2];
348 u32 tmca; /* Total number of frames that were transmitted
349 * succesfully with the group address bit set
350 * that are not broadcast frames */
351 u32 tbca; /* Total number of frames transmitted
352 * succesfully that had destination address
353 * field equal to the broadcast address */
354 u32 rxfok; /* Total number of frames received OK */
355 u32 rxbok; /* Total number of octets received OK */
356 u32 rbyt; /* Total number of octets received including
357 * octets in bad frames. Must be implemented
358 * in HW because it includes octets in frames
359 * that never even reach the UCC */
360 u32 rmca; /* Total number of frames that were received
361 * succesfully with the group address bit set
362 * that are not broadcast frames */
363 u32 rbca; /* Total number of frames received succesfully
364 * that had destination address equal to the
365 * broadcast address */
366 u32 scar; /* Statistics carry register */
367 u32 scam; /* Statistics caryy mask register */
368 u8 res5[0x200 - 0x1c4];
369 } __attribute__ ((packed)) uec_t;
371 /* QE UCC Fast */
372 typedef struct ucc_fast {
373 u32 gumr; /* UCCx general mode register */
374 u32 upsmr; /* UCCx protocol-specific mode register */
375 u16 utodr; /* UCCx transmit on demand register */
376 u8 res0[0x2];
377 u16 udsr; /* UCCx data synchronization register */
378 u8 res1[0x2];
379 u32 ucce; /* UCCx event register */
380 u32 uccm; /* UCCx mask register. */
381 u8 uccs; /* UCCx status register */
382 u8 res2[0x7];
383 u32 urfb; /* UCC receive FIFO base */
384 u16 urfs; /* UCC receive FIFO size */
385 u8 res3[0x2];
386 u16 urfet; /* UCC receive FIFO emergency threshold */
387 u16 urfset; /* UCC receive FIFO special emergency
388 * threshold */
389 u32 utfb; /* UCC transmit FIFO base */
390 u16 utfs; /* UCC transmit FIFO size */
391 u8 res4[0x2];
392 u16 utfet; /* UCC transmit FIFO emergency threshold */
393 u8 res5[0x2];
394 u16 utftt; /* UCC transmit FIFO transmit threshold */
395 u8 res6[0x2];
396 u16 utpt; /* UCC transmit polling timer */
397 u8 res7[0x2];
398 u32 urtry; /* UCC retry counter register */
399 u8 res8[0x4C];
400 u8 guemr; /* UCC general extended mode register */
401 u8 res9[0x100 - 0x091];
402 uec_t ucc_eth;
403 } __attribute__ ((packed)) ucc_fast_t;
405 /* QE UCC */
406 typedef struct ucc_common {
407 u8 res1[0x90];
408 u8 guemr;
409 u8 res2[0x200 - 0x091];
410 } __attribute__ ((packed)) ucc_common_t;
412 typedef struct ucc {
413 union {
414 ucc_slow_t slow;
415 ucc_fast_t fast;
416 ucc_common_t common;
417 };
418 } __attribute__ ((packed)) ucc_t;
420 /* MultiPHY UTOPIA POS Controllers (UPC) */
421 typedef struct upc {
422 u32 upgcr; /* UTOPIA/POS general configuration register */
423 u32 uplpa; /* UTOPIA/POS last PHY address */
424 u32 uphec; /* ATM HEC register */
425 u32 upuc; /* UTOPIA/POS UCC configuration */
426 u32 updc1; /* UTOPIA/POS device 1 configuration */
427 u32 updc2; /* UTOPIA/POS device 2 configuration */
428 u32 updc3; /* UTOPIA/POS device 3 configuration */
429 u32 updc4; /* UTOPIA/POS device 4 configuration */
430 u32 upstpa; /* UTOPIA/POS STPA threshold */
431 u8 res0[0xC];
432 u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
433 u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
434 u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
435 u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
436 u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
437 u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
438 u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
439 u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
440 u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
441 u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
442 u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
443 u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
444 u32 upde1; /* UTOPIA/POS device 1 event */
445 u32 upde2; /* UTOPIA/POS device 2 event */
446 u32 upde3; /* UTOPIA/POS device 3 event */
447 u32 upde4; /* UTOPIA/POS device 4 event */
448 u16 uprp1;
449 u16 uprp2;
450 u16 uprp3;
451 u16 uprp4;
452 u8 res1[0x8];
453 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
454 u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
455 u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
456 u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
457 u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
458 u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
459 u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
460 u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
461 u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
462 u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
463 u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
464 u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
465 u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
466 u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
467 u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
468 u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
469 u32 uper1; /* Device 1 port enable register */
470 u32 uper2; /* Device 2 port enable register */
471 u32 uper3; /* Device 3 port enable register */
472 u32 uper4; /* Device 4 port enable register */
473 u8 res2[0x150];
474 } __attribute__ ((packed)) upc_t;
476 /* SDMA */
477 typedef struct sdma {
478 u32 sdsr; /* Serial DMA status register */
479 u32 sdmr; /* Serial DMA mode register */
480 u32 sdtr1; /* SDMA system bus threshold register */
481 u32 sdtr2; /* SDMA secondary bus threshold register */
482 u32 sdhy1; /* SDMA system bus hysteresis register */
483 u32 sdhy2; /* SDMA secondary bus hysteresis register */
484 u32 sdta1; /* SDMA system bus address register */
485 u32 sdta2; /* SDMA secondary bus address register */
486 u32 sdtm1; /* SDMA system bus MSNUM register */
487 u32 sdtm2; /* SDMA secondary bus MSNUM register */
488 u8 res0[0x10];
489 u32 sdaqr; /* SDMA address bus qualify register */
490 u32 sdaqmr; /* SDMA address bus qualify mask register */
491 u8 res1[0x4];
492 u32 sdwbcr; /* SDMA CAM entries base register */
493 u8 res2[0x38];
494 } __attribute__ ((packed)) sdma_t;
496 /* Debug Space */
497 typedef struct dbg {
498 u32 bpdcr; /* Breakpoint debug command register */
499 u32 bpdsr; /* Breakpoint debug status register */
500 u32 bpdmr; /* Breakpoint debug mask register */
501 u32 bprmrr0; /* Breakpoint request mode risc register 0 */
502 u32 bprmrr1; /* Breakpoint request mode risc register 1 */
503 u8 res0[0x8];
504 u32 bprmtr0; /* Breakpoint request mode trb register 0 */
505 u32 bprmtr1; /* Breakpoint request mode trb register 1 */
506 u8 res1[0x8];
507 u32 bprmir; /* Breakpoint request mode immediate register */
508 u32 bprmsr; /* Breakpoint request mode serial register */
509 u32 bpemr; /* Breakpoint exit mode register */
510 u8 res2[0x48];
511 } __attribute__ ((packed)) dbg_t;
513 /*
514 * RISC Special Registers (Trap and Breakpoint). These are described in
515 * the QE Developer's Handbook.
516 */
517 typedef struct rsp {
518 u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
519 u8 res0[64];
520 u32 ibcr0;
521 u32 ibs0;
522 u32 ibcnr0;
523 u8 res1[4];
524 u32 ibcr1;
525 u32 ibs1;
526 u32 ibcnr1;
527 u32 npcr;
528 u32 dbcr;
529 u32 dbar;
530 u32 dbamr;
531 u32 dbsr;
532 u32 dbcnr;
533 u8 res2[12];
534 u32 dbdr_h;
535 u32 dbdr_l;
536 u32 dbdmr_h;
537 u32 dbdmr_l;
538 u32 bsr;
539 u32 bor;
540 u32 bior;
541 u8 res3[4];
542 u32 iatr[4];
543 u32 eccr; /* Exception control configuration register */
544 u32 eicr;
545 u8 res4[0x100-0xf8];
546 } __attribute__ ((packed)) rsp_t;
548 typedef struct qe_immap {
549 qe_iram_t iram; /* I-RAM */
550 qe_ic_t ic; /* Interrupt Controller */
551 cp_qe_t cp; /* Communications Processor */
552 qe_mux_t qmx; /* QE Multiplexer */
553 qe_timers_t qet; /* QE Timers */
554 spi_t spi[0x2]; /* spi */
555 mcc_t mcc; /* mcc */
556 qe_brg_t brg; /* brg */
557 usb_t usb; /* USB */
558 si1_t si1; /* SI */
559 u8 res11[0x800];
560 sir_t sir; /* SI Routing Tables */
561 ucc_t ucc1; /* ucc1 */
562 ucc_t ucc3; /* ucc3 */
563 ucc_t ucc5; /* ucc5 */
564 ucc_t ucc7; /* ucc7 */
565 u8 res12[0x600];
566 upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
567 ucc_t ucc2; /* ucc2 */
568 ucc_t ucc4; /* ucc4 */
569 ucc_t ucc6; /* ucc6 */
570 ucc_t ucc8; /* ucc8 */
571 u8 res13[0x600];
572 upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
573 sdma_t sdma; /* SDMA */
574 dbg_t dbg; /* Debug Space */
575 rsp_t rsp[0x2]; /* RISC Special Registers
576 * (Trap and Breakpoint) */
577 u8 res14[0x300];
578 u8 res15[0x3A00];
579 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
580 u8 muram[QE_MURAM_SIZE];
581 } __attribute__ ((packed)) qe_map_t;
583 extern qe_map_t *qe_immr;
585 #endif /* __IMMAP_QE_H__ */