1 /*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
24 * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
25 */
27 /*
28 * cpci750.c - main board support/init for the esd cpci750.
29 */
31 #include <common.h>
32 #include <command.h>
33 #include <74xx_7xx.h>
34 #include "../../Marvell/include/memory.h"
35 #include "../../Marvell/include/pci.h"
36 #include "../../Marvell/include/mv_gen_reg.h"
37 #include <net.h>
39 #include "eth.h"
40 #include "mpsc.h"
41 #include "i2c.h"
42 #include "64360.h"
43 #include "mv_regs.h"
45 #undef DEBUG
46 /*#define DEBUG */
48 #ifdef CONFIG_PCI
49 #define MAP_PCI
50 #endif /* of CONFIG_PCI */
52 #ifdef DEBUG
53 #define DP(x) x
54 #else
55 #define DP(x)
56 #endif
58 static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
59 {"PCI0DLL_1 "}, /* 30 */
60 {"PCI0DLL_0 "}, /* 29 */
61 {"PCI1DLL_2 "}, /* 28 */
62 {"PCI1DLL_1 "}, /* 27 */
63 {"PCI1DLL_0 "}, /* 26 */
64 {"BbEP2En "}, /* 25 */
65 {"SDRAMRdDataDel"}, /* 24 */
66 {"SDRAMRdDel "}, /* 23 */
67 {"SDRAMSync "}, /* 22 */
68 {"SDRAMPipeSel_1"}, /* 21 */
69 {"SDRAMPipeSel_0"}, /* 20 */
70 {"SDRAMAddDel "}, /* 19 */
71 {"SDRAMClkSel "}, /* 18 */
72 {"Reserved(1!) "}, /* 17 */
73 {"PCIRty "}, /* 16 */
74 {"BootCSWidth_1 "}, /* 15 */
75 {"BootCSWidth_0 "}, /* 14 */
76 {"PCI1PadsCal "}, /* 13 */
77 {"PCI0PadsCal "}, /* 12 */
78 {"MultiMVId_1 "}, /* 11 */
79 {"MultiMVId_0 "}, /* 10 */
80 {"MultiGTEn "}, /* 09 */
81 {"Int60xArb "}, /* 08 */
82 {"CPUBusConfig_1"}, /* 07 */
83 {"CPUBusConfig_0"}, /* 06 */
84 {"DefIntSpc "}, /* 05 */
85 {0 }, /* 04 */
86 {"SROMAdd_1 "}, /* 03 */
87 {"SROMAdd_0 "}, /* 02 */
88 {"DRAMPadCal "}, /* 01 */
89 {"SInitEn "}, /* 00 */
90 {0 }, /* 31 */
91 {0 }, /* 30 */
92 {0 }, /* 29 */
93 {0 }, /* 28 */
94 {0 }, /* 27 */
95 {0 }, /* 26 */
96 {0 }, /* 25 */
97 {0 }, /* 24 */
98 {0 }, /* 23 */
99 {0 }, /* 22 */
100 {"JTAGCalBy "}, /* 21 */
101 {"GB2Sel "}, /* 20 */
102 {"GB1Sel "}, /* 19 */
103 {"DRAMPLL_MDiv_5"}, /* 18 */
104 {"DRAMPLL_MDiv_4"}, /* 17 */
105 {"DRAMPLL_MDiv_3"}, /* 16 */
106 {"DRAMPLL_MDiv_2"}, /* 15 */
107 {"DRAMPLL_MDiv_1"}, /* 14 */
108 {"DRAMPLL_MDiv_0"}, /* 13 */
109 {"GB0Sel "}, /* 12 */
110 {"DRAMPLLPU "}, /* 11 */
111 {"DRAMPLL_HIKVCO"}, /* 10 */
112 {"DRAMPLLNP "}, /* 09 */
113 {"DRAMPLL_NDiv_7"}, /* 08 */
114 {"DRAMPLL_NDiv_6"}, /* 07 */
115 {"CPUPadCal "}, /* 06 */
116 {"DRAMPLL_NDiv_5"}, /* 05 */
117 {"DRAMPLL_NDiv_4"}, /* 04 */
118 {"DRAMPLL_NDiv_3"}, /* 03 */
119 {"DRAMPLL_NDiv_2"}, /* 02 */
120 {"DRAMPLL_NDiv_1"}, /* 01 */
121 {"DRAMPLL_NDiv_0"}}; /* 00 */
123 extern flash_info_t flash_info[];
125 extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
127 /* ------------------------------------------------------------------------- */
129 /* this is the current GT register space location */
130 /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
132 /* Unfortunately, we cant change it while we are in flash, so we initialize it
133 * to the "final" value. This means that any debug_led calls before
134 * board_early_init_f wont work right (like in cpu_init_f).
135 * See also my_remap_gt_regs below. (NTL)
136 */
138 void board_prebootm_init (void);
139 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
140 int display_mem_map (void);
142 /*
143 * Skip video initialization on slave variant.
144 * This function will overwrite the weak default in cfb_console.c
145 */
146 int board_video_skip(void)
147 {
148 return CPCI750_SLAVE_TEST;
149 }
151 /* ------------------------------------------------------------------------- */
153 /*
154 * This is a version of the GT register space remapping function that
155 * doesn't touch globals (meaning, it's ok to run from flash.)
156 *
157 * Unfortunately, this has the side effect that a writable
158 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
159 */
161 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
162 {
163 u32 temp;
165 /* check and see if it's already moved */
167 /* original ppcboot 1.1.6 source
169 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
170 if ((temp & 0xffff) == new_loc >> 20)
171 return;
173 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
174 0xffff0000) | (new_loc >> 20);
176 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
178 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
179 original ppcboot 1.1.6 source end */
181 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
182 if ((temp & 0xffff) == new_loc >> 16)
183 return;
185 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
186 0xffff0000) | (new_loc >> 16);
188 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
190 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
191 }
193 #ifdef CONFIG_PCI
195 static void gt_pci_config (void)
196 {
197 unsigned int stat;
198 unsigned int data;
199 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
201 /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
202 * config registers by writing ones to the bus and device.
203 * We then update the Virtual register with the correct value for the bus and device.
204 */
205 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
206 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
208 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
210 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
211 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
212 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
214 }
215 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
216 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
217 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
219 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
220 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
221 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
222 }
224 /* Enable master */
225 PCI_MASTER_ENABLE (0, SELF);
226 PCI_MASTER_ENABLE (1, SELF);
228 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
229 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
230 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
231 <<
232 18);
233 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
234 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
236 /* ronen- add write to pci remap registers for 64460.
237 in 64360 when writing to pci base go and overide remap automaticaly,
238 in 64460 it doesn't */
239 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
240 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
241 GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
243 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
244 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
245 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
247 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
248 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
249 GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
251 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
252 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
253 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
255 /* PCI interface settings */
256 /* Timeout set to retry forever */
257 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
258 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
260 /* ronen - enable only CS0 and Internal reg!! */
261 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
262 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
264 /*ronen update the pci internal registers base address.*/
265 #ifdef MAP_PCI
266 for (stat = 0; stat <= PCI_HOST1; stat++) {
267 data = pciReadConfigReg(stat,
268 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
269 SELF);
270 data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
271 pciWriteConfigReg (stat,
272 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
273 SELF, data);
274 }
275 #endif
277 }
278 #endif
280 /* Setup CPU interface paramaters */
281 static void gt_cpu_config (void)
282 {
283 cpu_t cpu = get_cpu_type ();
284 ulong tmp;
286 /* cpu configuration register */
287 tmp = GTREGREAD (CPU_CONFIGURATION);
289 /* set the SINGLE_CPU bit see MV64360 P.399 */
290 #ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
291 tmp |= CPU_CONF_SINGLE_CPU;
292 #endif
294 tmp &= ~CPU_CONF_AACK_DELAY_2;
296 tmp |= CPU_CONF_DP_VALID;
297 tmp |= CPU_CONF_AP_VALID;
299 tmp |= CPU_CONF_PIPELINE;
301 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
303 /* CPU master control register */
304 tmp = GTREGREAD (CPU_MASTER_CONTROL);
306 tmp |= CPU_MAST_CTL_ARB_EN;
308 if ((cpu == CPU_7400) ||
309 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
311 tmp |= CPU_MAST_CTL_CLEAN_BLK;
312 tmp |= CPU_MAST_CTL_FLUSH_BLK;
314 } else {
315 /* cleanblock must be cleared for CPUs
316 * that do not support this command (603e, 750)
317 * see Res#1 */
318 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
319 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
320 }
321 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
322 }
324 /*
325 * board_early_init_f.
326 *
327 * set up gal. device mappings, etc.
328 */
329 int board_early_init_f (void)
330 {
332 /*
333 * set up the GT the way the kernel wants it
334 * the call to move the GT register space will obviously
335 * fail if it has already been done, but we're going to assume
336 * that if it's not at the power-on location, it's where we put
337 * it last time. (huber)
338 */
340 my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
342 /* No PCI in first release of Port To_do: enable it. */
343 #ifdef CONFIG_PCI
344 gt_pci_config ();
345 #endif
346 /* mask all external interrupt sources */
347 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
348 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
349 /* new in MV6436x */
350 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
351 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
352 /* --------------------- */
353 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
354 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
355 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
356 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
357 /* does not exist in MV6436x
358 GT_REG_WRITE(CPU_INT_0_MASK, 0);
359 GT_REG_WRITE(CPU_INT_1_MASK, 0);
360 GT_REG_WRITE(CPU_INT_2_MASK, 0);
361 GT_REG_WRITE(CPU_INT_3_MASK, 0);
362 --------------------- */
365 /* ----- DEVICE BUS SETTINGS ------ */
367 /*
368 * EVB
369 * 0 - SRAM ????
370 * 1 - RTC ????
371 * 2 - UART ????
372 * 3 - Flash checked 32Bit Intel Strata
373 * boot - BootCS checked 8Bit 29LV040B
374 *
375 */
377 /*
378 * the dual 7450 module requires burst access to the boot
379 * device, so the serial rom copies the boot device to the
380 * on-board sram on the eval board, and updates the correct
381 * registers to boot from the sram. (device0)
382 */
384 memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
385 memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
386 memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
387 memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
390 /* configure device timing */
391 GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
392 GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
393 GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
394 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
396 #ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
397 /* detect if we are booting from the 32 bit flash */
398 if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
399 /* 32 bit boot flash */
400 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
401 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
402 CONFIG_SYS_32BIT_BOOT_PAR);
403 } else {
404 /* 8 bit boot flash */
405 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
406 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
407 }
408 #else
409 /* 8 bit boot flash only */
410 /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
411 #endif
414 gt_cpu_config ();
416 /* MPP setup */
417 GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
418 GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
419 GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
420 GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
422 GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
423 DEBUG_LED0_ON ();
424 DEBUG_LED1_ON ();
425 DEBUG_LED2_ON ();
427 return 0;
428 }
430 /* various things to do after relocation */
432 int misc_init_r ()
433 {
434 icache_enable ();
435 #ifdef CONFIG_SYS_L2
436 l2cache_enable ();
437 #endif
438 #ifdef CONFIG_MPSC
440 mpsc_sdma_init ();
441 mpsc_init2 ();
442 #endif
444 #if 0
445 /* disable the dcache and MMU */
446 dcache_lock ();
447 #endif
448 if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
449 unsigned int flash_offset;
450 unsigned int l;
452 flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
453 for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
454 if (flash_info[3].start[l] != 0) {
455 flash_info[3].start[l] += flash_offset;
456 }
457 }
458 flash_protect (FLAG_PROTECT_SET,
459 CONFIG_SYS_MONITOR_BASE,
460 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
461 &flash_info[3]);
462 }
463 return 0;
464 }
466 void after_reloc (ulong dest_addr, gd_t * gd)
467 {
468 memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
469 CONFIG_SYS_BOOT_SIZE);
471 display_mem_map ();
472 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
473 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
475 /* now, jump to the main ppcboot board init code */
476 board_init_r (gd, dest_addr);
477 /* NOTREACHED */
478 }
480 /* ------------------------------------------------------------------------- */
482 /*
483 * Check Board Identity:
484 *
485 * right now, assume borad type. (there is just one...after all)
486 */
488 int checkboard (void)
489 {
490 int l_type = 0;
492 printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
493 return (l_type);
494 }
496 /* utility functions */
497 void debug_led (int led, int mode)
498 {
499 }
501 int display_mem_map (void)
502 {
503 int i, j;
504 unsigned int base, size, width;
506 /* SDRAM */
507 printf ("SD (DDR) RAM\n");
508 for (i = 0; i <= BANK3; i++) {
509 base = memoryGetBankBaseAddress (i);
510 size = memoryGetBankSize (i);
511 if (size != 0) {
512 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
513 i, base, size >> 20);
514 }
515 }
516 #ifdef CONFIG_PCI
517 /* CPU's PCI windows */
518 for (i = 0; i <= PCI_HOST1; i++) {
519 printf ("\nCPU's PCI %d windows\n", i);
520 base = pciGetSpaceBase (i, PCI_IO);
521 size = pciGetSpaceSize (i, PCI_IO);
522 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
523 size >> 20);
524 for (j = 0;
525 j <=
526 PCI_REGION0
527 /*ronen currently only first PCI MEM is used 3 */ ;
528 j++) {
529 base = pciGetSpaceBase (i, j);
530 size = pciGetSpaceSize (i, j);
531 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
532 }
533 }
534 #endif /* of CONFIG_PCI */
535 /* Devices */
536 printf ("\nDEVICES\n");
537 for (i = 0; i <= DEVICE3; i++) {
538 base = memoryGetDeviceBaseAddress (i);
539 size = memoryGetDeviceSize (i);
540 width = memoryGetDeviceWidth (i) * 8;
541 printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
542 if (i == 0)
543 printf ("\t- FLASH\n");
544 else if (i == 1)
545 printf ("\t- FLASH\n");
546 else if (i == 2)
547 printf ("\t- FLASH\n");
548 else
549 printf ("\t- RTC/REGS/CAN\n");
550 }
552 /* Bootrom */
553 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
554 size = memoryGetDeviceSize (BOOT_DEVICE);
555 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
556 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
557 base, size >> 20, width);
558 return (0);
559 }
561 /*
562 * Command loadpci: wait for signal from host and boot image.
563 */
564 int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
565 {
566 volatile unsigned int *ptr;
567 int count = 0;
568 int count2 = 0;
569 int status = 0;
570 char addr[16];
571 char str[] = "\\|/-";
572 char *local_args[2];
574 /*
575 * Mark sync address
576 */
577 ptr = 0;
578 ptr[0] = 0xffffffff;
579 ptr[1] = 0xffffffff;
580 puts("\nWaiting for image from pci host -");
582 /*
583 * Wait for host to write the start address
584 */
585 while (*ptr == 0xffffffff) {
586 count++;
587 if (!(count % 100)) {
588 count2++;
589 putc(0x08); /* backspace */
590 putc(str[count2 % 4]);
591 }
593 /* Abort if ctrl-c was pressed */
594 if (ctrlc()) {
595 puts("\nAbort\n");
596 return 0;
597 }
599 udelay(1000);
600 }
602 sprintf(addr, "%08x", *ptr);
603 printf("\nBooting Image at addr 0x%s ...\n", addr);
604 setenv("loadaddr", addr);
606 switch (ptr[1] == 0) {
607 case 0:
608 /*
609 * Boot image via bootm
610 */
611 local_args[0] = argv[0];
612 local_args[1] = NULL;
613 status = do_bootm (cmdtp, 0, 1, local_args);
614 break;
615 case 1:
616 /*
617 * Boot image via bootvx
618 */
619 local_args[0] = argv[0];
620 local_args[1] = NULL;
621 status = do_bootvx (cmdtp, 0, 1, local_args);
622 break;
623 }
625 return status;
626 }
628 U_BOOT_CMD(
629 loadpci, 1, 1, do_loadpci,
630 "loadpci - Wait for pci-image and boot it\n",
631 NULL
632 );
634 /* DRAM check routines copied from gw8260 */
636 #if defined (CONFIG_SYS_DRAM_TEST)
638 /*********************************************************************/
639 /* NAME: move64() - moves a double word (64-bit) */
640 /* */
641 /* DESCRIPTION: */
642 /* this function performs a double word move from the data at */
643 /* the source pointer to the location at the destination pointer. */
644 /* */
645 /* INPUTS: */
646 /* unsigned long long *src - pointer to data to move */
647 /* */
648 /* OUTPUTS: */
649 /* unsigned long long *dest - pointer to locate to move data */
650 /* */
651 /* RETURNS: */
652 /* None */
653 /* */
654 /* RESTRICTIONS/LIMITATIONS: */
655 /* May cloober fr0. */
656 /* */
657 /*********************************************************************/
658 static void move64 (unsigned long long *src, unsigned long long *dest)
659 {
660 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
661 "stfd 0, 0(4)" /* *dest = fpr0 */
662 : : : "fr0"); /* Clobbers fr0 */
663 return;
664 }
667 #if defined (CONFIG_SYS_DRAM_TEST_DATA)
669 unsigned long long pattern[] = {
670 0xaaaaaaaaaaaaaaaaLL,
671 0xccccccccccccccccLL,
672 0xf0f0f0f0f0f0f0f0LL,
673 0xff00ff00ff00ff00LL,
674 0xffff0000ffff0000LL,
675 0xffffffff00000000LL,
676 0x00000000ffffffffLL,
677 0x0000ffff0000ffffLL,
678 0x00ff00ff00ff00ffLL,
679 0x0f0f0f0f0f0f0f0fLL,
680 0x3333333333333333LL,
681 0x5555555555555555LL,
682 };
684 /*********************************************************************/
685 /* NAME: mem_test_data() - test data lines for shorts and opens */
686 /* */
687 /* DESCRIPTION: */
688 /* Tests data lines for shorts and opens by forcing adjacent data */
689 /* to opposite states. Because the data lines could be routed in */
690 /* an arbitrary manner the must ensure test patterns ensure that */
691 /* every case is tested. By using the following series of binary */
692 /* patterns every combination of adjacent bits is test regardless */
693 /* of routing. */
694 /* */
695 /* ...101010101010101010101010 */
696 /* ...110011001100110011001100 */
697 /* ...111100001111000011110000 */
698 /* ...111111110000000011111111 */
699 /* */
700 /* Carrying this out, gives us six hex patterns as follows: */
701 /* */
702 /* 0xaaaaaaaaaaaaaaaa */
703 /* 0xcccccccccccccccc */
704 /* 0xf0f0f0f0f0f0f0f0 */
705 /* 0xff00ff00ff00ff00 */
706 /* 0xffff0000ffff0000 */
707 /* 0xffffffff00000000 */
708 /* */
709 /* The number test patterns will always be given by: */
710 /* */
711 /* log(base 2)(number data bits) = log2 (64) = 6 */
712 /* */
713 /* To test for short and opens to other signals on our boards. we */
714 /* simply */
715 /* test with the 1's complemnt of the paterns as well. */
716 /* */
717 /* OUTPUTS: */
718 /* Displays failing test pattern */
719 /* */
720 /* RETURNS: */
721 /* 0 - Passed test */
722 /* 1 - Failed test */
723 /* */
724 /* RESTRICTIONS/LIMITATIONS: */
725 /* Assumes only one one SDRAM bank */
726 /* */
727 /*********************************************************************/
728 int mem_test_data (void)
729 {
730 unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
731 unsigned long long temp64 = 0;
732 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
733 int i;
734 unsigned int hi, lo;
736 for (i = 0; i < num_patterns; i++) {
737 move64 (&(pattern[i]), pmem);
738 move64 (pmem, &temp64);
740 /* hi = (temp64>>32) & 0xffffffff; */
741 /* lo = temp64 & 0xffffffff; */
742 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
744 hi = (pattern[i] >> 32) & 0xffffffff;
745 lo = pattern[i] & 0xffffffff;
746 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
748 if (temp64 != pattern[i]) {
749 printf ("\n Data Test Failed, pattern 0x%08x%08x",
750 hi, lo);
751 return 1;
752 }
753 }
755 return 0;
756 }
757 #endif /* CONFIG_SYS_DRAM_TEST_DATA */
759 #if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
760 /*********************************************************************/
761 /* NAME: mem_test_address() - test address lines */
762 /* */
763 /* DESCRIPTION: */
764 /* This function performs a test to verify that each word im */
765 /* memory is uniquly addressable. The test sequence is as follows: */
766 /* */
767 /* 1) write the address of each word to each word. */
768 /* 2) verify that each location equals its address */
769 /* */
770 /* OUTPUTS: */
771 /* Displays failing test pattern and address */
772 /* */
773 /* RETURNS: */
774 /* 0 - Passed test */
775 /* 1 - Failed test */
776 /* */
777 /* RESTRICTIONS/LIMITATIONS: */
778 /* */
779 /* */
780 /*********************************************************************/
781 int mem_test_address (void)
782 {
783 volatile unsigned int *pmem =
784 (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
785 const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
786 unsigned int i;
788 /* write address to each location */
789 for (i = 0; i < size; i++) {
790 pmem[i] = i;
791 }
793 /* verify each loaction */
794 for (i = 0; i < size; i++) {
795 if (pmem[i] != i) {
796 printf ("\n Address Test Failed at 0x%x", i);
797 return 1;
798 }
799 }
800 return 0;
801 }
802 #endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
804 #if defined (CONFIG_SYS_DRAM_TEST_WALK)
805 /*********************************************************************/
806 /* NAME: mem_march() - memory march */
807 /* */
808 /* DESCRIPTION: */
809 /* Marches up through memory. At each location verifies rmask if */
810 /* read = 1. At each location write wmask if write = 1. Displays */
811 /* failing address and pattern. */
812 /* */
813 /* INPUTS: */
814 /* volatile unsigned long long * base - start address of test */
815 /* unsigned int size - number of dwords(64-bit) to test */
816 /* unsigned long long rmask - read verify mask */
817 /* unsigned long long wmask - wrtie verify mask */
818 /* short read - verifies rmask if read = 1 */
819 /* short write - writes wmask if write = 1 */
820 /* */
821 /* OUTPUTS: */
822 /* Displays failing test pattern and address */
823 /* */
824 /* RETURNS: */
825 /* 0 - Passed test */
826 /* 1 - Failed test */
827 /* */
828 /* RESTRICTIONS/LIMITATIONS: */
829 /* */
830 /* */
831 /*********************************************************************/
832 int mem_march (volatile unsigned long long *base,
833 unsigned int size,
834 unsigned long long rmask,
835 unsigned long long wmask, short read, short write)
836 {
837 unsigned int i;
838 unsigned long long temp = 0;
839 unsigned int hitemp, lotemp, himask, lomask;
841 for (i = 0; i < size; i++) {
842 if (read != 0) {
843 /* temp = base[i]; */
844 move64 ((unsigned long long *) &(base[i]), &temp);
845 if (rmask != temp) {
846 hitemp = (temp >> 32) & 0xffffffff;
847 lotemp = temp & 0xffffffff;
848 himask = (rmask >> 32) & 0xffffffff;
849 lomask = rmask & 0xffffffff;
851 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
852 return 1;
853 }
854 }
855 if (write != 0) {
856 /* base[i] = wmask; */
857 move64 (&wmask, (unsigned long long *) &(base[i]));
858 }
859 }
860 return 0;
861 }
862 #endif /* CONFIG_SYS_DRAM_TEST_WALK */
864 /*********************************************************************/
865 /* NAME: mem_test_walk() - a simple walking ones test */
866 /* */
867 /* DESCRIPTION: */
868 /* Performs a walking ones through entire physical memory. The */
869 /* test uses as series of memory marches, mem_march(), to verify */
870 /* and write the test patterns to memory. The test sequence is as */
871 /* follows: */
872 /* 1) march writing 0000...0001 */
873 /* 2) march verifying 0000...0001 , writing 0000...0010 */
874 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
875 /* the write mask equals 1000...0000 */
876 /* 4) march verifying 1000...0000 */
877 /* The test fails if any of the memory marches return a failure. */
878 /* */
879 /* OUTPUTS: */
880 /* Displays which pass on the memory test is executing */
881 /* */
882 /* RETURNS: */
883 /* 0 - Passed test */
884 /* 1 - Failed test */
885 /* */
886 /* RESTRICTIONS/LIMITATIONS: */
887 /* */
888 /* */
889 /*********************************************************************/
890 int mem_test_walk (void)
891 {
892 unsigned long long mask;
893 volatile unsigned long long *pmem =
894 (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
895 const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
897 unsigned int i;
899 mask = 0x01;
901 printf ("Initial Pass");
902 mem_march (pmem, size, 0x0, 0x1, 0, 1);
904 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
905 printf (" ");
906 printf (" ");
907 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
909 for (i = 0; i < 63; i++) {
910 printf ("Pass %2d", i + 2);
911 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
912 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
913 return 1;
914 }
915 mask = mask << 1;
916 printf ("\b\b\b\b\b\b\b");
917 }
919 printf ("Last Pass");
920 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
921 /* printf("mask: 0x%x", mask); */
922 return 1;
923 }
924 printf ("\b\b\b\b\b\b\b\b\b");
925 printf (" ");
926 printf ("\b\b\b\b\b\b\b\b\b");
928 return 0;
929 }
931 /*********************************************************************/
932 /* NAME: testdram() - calls any enabled memory tests */
933 /* */
934 /* DESCRIPTION: */
935 /* Runs memory tests if the environment test variables are set to */
936 /* 'y'. */
937 /* */
938 /* INPUTS: */
939 /* testdramdata - If set to 'y', data test is run. */
940 /* testdramaddress - If set to 'y', address test is run. */
941 /* testdramwalk - If set to 'y', walking ones test is run */
942 /* */
943 /* OUTPUTS: */
944 /* None */
945 /* */
946 /* RETURNS: */
947 /* 0 - Passed test */
948 /* 1 - Failed test */
949 /* */
950 /* RESTRICTIONS/LIMITATIONS: */
951 /* */
952 /* */
953 /*********************************************************************/
954 int testdram (void)
955 {
956 char *s;
957 int rundata = 0;
958 int runaddress = 0;
959 int runwalk = 0;
961 #ifdef CONFIG_SYS_DRAM_TEST_DATA
962 s = getenv ("testdramdata");
963 rundata = (s && (*s == 'y')) ? 1 : 0;
964 #endif
965 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
966 s = getenv ("testdramaddress");
967 runaddress = (s && (*s == 'y')) ? 1 : 0;
968 #endif
969 #ifdef CONFIG_SYS_DRAM_TEST_WALK
970 s = getenv ("testdramwalk");
971 runwalk = (s && (*s == 'y')) ? 1 : 0;
972 #endif
974 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
975 printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
976 }
977 #ifdef CONFIG_SYS_DRAM_TEST_DATA
978 if (rundata == 1) {
979 printf ("Test DATA ... ");
980 if (mem_test_data () == 1) {
981 printf ("failed \n");
982 return 1;
983 } else
984 printf ("ok \n");
985 }
986 #endif
987 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
988 if (runaddress == 1) {
989 printf ("Test ADDRESS ... ");
990 if (mem_test_address () == 1) {
991 printf ("failed \n");
992 return 1;
993 } else
994 printf ("ok \n");
995 }
996 #endif
997 #ifdef CONFIG_SYS_DRAM_TEST_WALK
998 if (runwalk == 1) {
999 printf ("Test WALKING ONEs ... ");
1000 if (mem_test_walk () == 1) {
1001 printf ("failed \n");
1002 return 1;
1003 } else
1004 printf ("ok \n");
1005 }
1006 #endif
1007 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
1008 printf ("passed\n");
1009 }
1010 return 0;
1012 }
1013 #endif /* CONFIG_SYS_DRAM_TEST */
1015 /* ronen - the below functions are used by the bootm function */
1016 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
1017 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
1018 /* the kernel data areas. */
1019 /* - we diable and invalidate the icache and dcache. */
1020 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
1021 {
1022 u32 temp;
1024 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
1025 if ((temp & 0xffff) == new_loc >> 16)
1026 return;
1028 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
1029 0xffff0000) | (new_loc >> 16);
1031 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
1033 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
1034 new_loc |
1035 (INTERNAL_SPACE_DECODE)))))
1036 != temp);
1038 }
1040 void board_prebootm_init ()
1041 {
1043 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
1044 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
1046 /* Stop GigE Rx DMA engines */
1047 GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
1048 /* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
1049 /* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
1051 /* Relocate MV64360 internal regs */
1052 my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
1054 icache_disable ();
1055 dcache_disable ();
1056 }
1058 int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1059 {
1060 unsigned int reset_sample_low;
1061 unsigned int reset_sample_high;
1062 unsigned int l, l1, l2;
1064 GT_REG_READ(0x3c4, &reset_sample_low);
1065 GT_REG_READ(0x3d4, &reset_sample_high);
1066 printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
1068 l2 = 0;
1069 for (l=0; l<63; l++) {
1070 if (show_config_tab[l][0] != 0) {
1071 printf("%14s:%1x ", show_config_tab[l],
1072 ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
1073 l2++;
1074 if ((l2 % 4) == 0)
1075 printf("\n");
1076 } else {
1077 l1++;
1078 }
1079 if (l == 32)
1080 reset_sample_low = reset_sample_high;
1081 }
1082 printf("\n");
1084 return(0);
1085 }
1087 U_BOOT_CMD(
1088 show_config, 1, 1, do_show_config,
1089 "Show Marvell strapping register",
1090 "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
1091 );
1093 int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1094 {
1095 printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
1097 return 0;
1098 }
1100 U_BOOT_CMD(
1101 pldver, 1, 1, do_pldver,
1102 "Show PLD version",
1103 "Show PLD version)");
1105 int board_eth_init(bd_t *bis)
1106 {
1107 return mv6436x_eth_initialize(bis);
1108 }