1 /*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
25 #include <common.h>
26 #include <command.h>
27 #include <pci.h>
28 #include <asm/io.h>
30 #define OK 0
31 #define ERROR (-1)
33 #define TRUE 1
34 #define FALSE 0
37 extern u_long pci9054_iobase;
40 /***************************************************************************
41 *
42 * Routines for PLX PCI9054 eeprom access
43 *
44 */
46 static unsigned int PciEepromReadLongVPD (int offs)
47 {
48 unsigned int value;
49 unsigned int ret;
50 int count;
52 pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
53 (offs << 16) | 0x0003);
54 count = 0;
56 for (;;) {
57 udelay (10 * 1000);
58 pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
59 if ((ret & 0x80000000) != 0) {
60 break;
61 } else {
62 count++;
63 if (count > 10) {
64 printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
65 break;
66 }
67 }
68 }
70 pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
72 return value;
73 }
76 static int PciEepromWriteLongVPD (int offs, unsigned int value)
77 {
78 unsigned int ret;
79 int count;
81 pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
82 pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
83 (offs << 16) | 0x80000003);
84 count = 0;
86 for (;;) {
87 udelay (10 * 1000);
88 pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
89 if ((ret & 0x80000000) == 0) {
90 break;
91 } else {
92 count++;
93 if (count > 10) {
94 printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
95 break;
96 }
97 }
98 }
100 return TRUE;
101 }
104 static void showPci9054 (void)
105 {
106 int val;
107 int l, i;
109 /* read 9054-values */
110 for (l = 0; l < 6; l++) {
111 printf ("%02x: ", l * 0x10);
112 for (i = 0; i < 4; i++) {
113 pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
114 l * 16 + i * 4,
115 (unsigned int *)&val);
116 printf ("%08x ", val);
117 }
118 printf ("\n");
119 }
120 printf ("\n");
122 for (l = 0; l < 7; l++) {
123 printf ("%02x: ", l * 0x10);
124 for (i = 0; i < 4; i++)
125 printf ("%08x ",
126 PciEepromReadLongVPD ((i + l * 4) * 4));
127 printf ("\n");
128 }
129 printf ("\n");
130 }
133 static void updatePci9054 (void)
134 {
135 /*
136 * Set EEPROM write-protect register to 0
137 */
138 out_be32 ((void *)(pci9054_iobase + 0x0c),
139 in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
141 /* Long Serial EEPROM Load Registers... */
142 PciEepromWriteLongVPD (0x00, 0x905410b5);
143 PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
144 PciEepromWriteLongVPD (0x08, 0x28140100);
146 PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
147 PciEepromWriteLongVPD (0x10, 0x00000000);
149 /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
150 PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
151 PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
153 PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
154 PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
156 PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
157 PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
159 PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
161 PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
162 PciEepromWriteLongVPD (0x34, 0x00000000);
163 PciEepromWriteLongVPD (0x38, 0x00000000);
165 PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
166 PciEepromWriteLongVPD (0x40, 0x00000000);
168 /* Extra Long Serial EEPROM Load Registers... */
169 PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
171 /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
172 /* Offset to LAS1: Group 1: 0x00040000 */
173 /* Group 2: 0x00080000 */
174 /* Group 3: 0x000c0000 */
175 PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
176 PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
177 PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
179 PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
181 printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
182 }
185 static void clearPci9054 (void)
186 {
187 /*
188 * Set EEPROM write-protect register to 0
189 */
190 out_be32 ((void *)(pci9054_iobase + 0x0c),
191 in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
193 /* Long Serial EEPROM Load Registers... */
194 PciEepromWriteLongVPD (0x00, 0xffffffff);
195 PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
197 printf ("Finished clearing PLX PCI9054 EEPROM!\n");
198 }
201 /* ------------------------------------------------------------------------- */
202 int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
203 char * const argv[])
204 {
205 if (strcmp (argv[1], "info") == 0) {
206 showPci9054 ();
207 return 0;
208 }
210 if (strcmp (argv[1], "update") == 0) {
211 updatePci9054 ();
212 return 0;
213 }
215 if (strcmp (argv[1], "clear") == 0) {
216 clearPci9054 ();
217 return 0;
218 }
220 return cmd_usage(cmdtp);
221 }
223 U_BOOT_CMD(
224 pci9054, 3, 1, do_pci9054,
225 "PLX PCI9054 EEPROM access",
226 "pci9054 info - print EEPROM values\n"
227 "pci9054 update - updates EEPROM with default values"
228 );
230 /* ------------------------------------------------------------------------- */