mx51evk: Add DVI output support
[glsdk/glsdk-u-boot.git] / board / freescale / mx51evk / mx51evk.c
1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/gpio.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
32 #include <asm/arch/clock.h>
33 #include <asm/imx-common/mx5_video.h>
34 #include <i2c.h>
35 #include <mmc.h>
36 #include <fsl_esdhc.h>
37 #include <power/pmic.h>
38 #include <fsl_pmic.h>
39 #include <mc13892.h>
40 #include <usb/ehci-fsl.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 #ifdef CONFIG_FSL_ESDHC
45 struct fsl_esdhc_cfg esdhc_cfg[2] = {
46         {MMC_SDHC1_BASE_ADDR},
47         {MMC_SDHC2_BASE_ADDR},
48 };
49 #endif
51 int dram_init(void)
52 {
53         /* dram_init must store complete ramsize in gd->ram_size */
54         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
55                                 PHYS_SDRAM_1_SIZE);
56         return 0;
57 }
59 u32 get_board_rev(void)
60 {
61         u32 rev = get_cpu_rev();
62         if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
63                 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
64         return rev;
65 }
67 static void setup_iomux_uart(void)
68 {
69         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
70                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
72         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
73         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
74         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
75         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
76         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
77         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
78         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
79         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
80 }
82 static void setup_iomux_fec(void)
83 {
84         /*FEC_MDIO*/
85         mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
86         mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
88         /*FEC_MDC*/
89         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
90         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
92         /* FEC RDATA[3] */
93         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
94         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
96         /* FEC RDATA[2] */
97         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
98         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
100         /* FEC RDATA[1] */
101         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
102         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
104         /* FEC RDATA[0] */
105         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
106         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
108         /* FEC TDATA[3] */
109         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
110         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
112         /* FEC TDATA[2] */
113         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
114         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
116         /* FEC TDATA[1] */
117         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
118         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
120         /* FEC TDATA[0] */
121         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
122         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
124         /* FEC TX_EN */
125         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
126         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
128         /* FEC TX_ER */
129         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
130         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
132         /* FEC TX_CLK */
133         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
134         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
136         /* FEC TX_COL */
137         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
138         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
140         /* FEC RX_CLK */
141         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
142         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
144         /* FEC RX_CRS */
145         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
146         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
148         /* FEC RX_ER */
149         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
150         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
152         /* FEC RX_DV */
153         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
154         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
157 #ifdef CONFIG_MXC_SPI
158 static void setup_iomux_spi(void)
160         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
161         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
162         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
164         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
165         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
166         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
168         /* de-select SS1 of instance: ecspi1. */
169         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
170         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
172         /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
173         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
174         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
176         /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
177         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
178         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
180         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
181         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
182         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
184 #endif
186 #ifdef CONFIG_USB_EHCI_MX5
187 #define MX51EVK_USBH1_HUB_RST   IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
188 #define MX51EVK_USBH1_STP       IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
189 #define MX51EVK_USB_CLK_EN_B    IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
190 #define MX51EVK_USB_PHY_RESET   IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
192 #define USBH1_PAD       (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |          \
193                          PAD_CTL_100K_PU | PAD_CTL_PUE_PULL |           \
194                          PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
195 #define GPIO_PAD        (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE |        \
196                          PAD_CTL_SRE_FAST)
197 #define NO_PAD          (1 << 16)
199 static void setup_usb_h1(void)
201         setup_iomux_usb_h1();
203         /* GPIO_1_7 for USBH1 hub reset */
204         mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
205         mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
207         /* GPIO_2_1 */
208         mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
209         mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
211         /* GPIO_2_5 for USB PHY reset */
212         mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
213         mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
216 int board_ehci_hcd_init(int port)
218         /* Set USBH1_STP to GPIO and toggle it */
219         mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
220         mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
222         gpio_direction_output(MX51EVK_USBH1_STP, 0);
223         gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
224         mdelay(10);
225         gpio_set_value(MX51EVK_USBH1_STP, 1);
227         /* Set back USBH1_STP to be function */
228         mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
229         mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
231         /* De-assert USB PHY RESETB */
232         gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
234         /* Drive USB_CLK_EN_B line low */
235         gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
237         /* Reset USB hub */
238         gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
239         mdelay(2);
240         gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
241         return 0;
243 #endif
245 static void power_init(void)
247         unsigned int val;
248         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
249         struct pmic *p;
250         int ret;
252         ret = pmic_init(I2C_PMIC);
253         if (ret)
254                 return;
256         p = pmic_get("FSL_PMIC");
257         if (!p)
258                 return;
260         /* Write needed to Power Gate 2 register */
261         pmic_reg_read(p, REG_POWER_MISC, &val);
262         val &= ~PWGT2SPIEN;
263         pmic_reg_write(p, REG_POWER_MISC, val);
265         /* Externally powered */
266         pmic_reg_read(p, REG_CHARGE, &val);
267         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
268         pmic_reg_write(p, REG_CHARGE, val);
270         /* power up the system first */
271         pmic_reg_write(p, REG_POWER_MISC, PWUP);
273         /* Set core voltage to 1.1V */
274         pmic_reg_read(p, REG_SW_0, &val);
275         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
276         pmic_reg_write(p, REG_SW_0, val);
278         /* Setup VCC (SW2) to 1.25 */
279         pmic_reg_read(p, REG_SW_1, &val);
280         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
281         pmic_reg_write(p, REG_SW_1, val);
283         /* Setup 1V2_DIG1 (SW3) to 1.25 */
284         pmic_reg_read(p, REG_SW_2, &val);
285         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
286         pmic_reg_write(p, REG_SW_2, val);
287         udelay(50);
289         /* Raise the core frequency to 800MHz */
290         writel(0x0, &mxc_ccm->cacrr);
292         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
293         /* Setup the switcher mode for SW1 & SW2*/
294         pmic_reg_read(p, REG_SW_4, &val);
295         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
296                 (SWMODE_MASK << SWMODE2_SHIFT)));
297         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
298                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
299         pmic_reg_write(p, REG_SW_4, val);
301         /* Setup the switcher mode for SW3 & SW4 */
302         pmic_reg_read(p, REG_SW_5, &val);
303         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
304                 (SWMODE_MASK << SWMODE4_SHIFT)));
305         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
306                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
307         pmic_reg_write(p, REG_SW_5, val);
309         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
310         pmic_reg_read(p, REG_SETTING_0, &val);
311         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
312         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
313         pmic_reg_write(p, REG_SETTING_0, val);
315         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
316         pmic_reg_read(p, REG_SETTING_1, &val);
317         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
318         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
319         pmic_reg_write(p, REG_SETTING_1, val);
321         /* Configure VGEN3 and VCAM regulators to use external PNP */
322         val = VGEN3CONFIG | VCAMCONFIG;
323         pmic_reg_write(p, REG_MODE_1, val);
324         udelay(200);
326         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
327         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
328                 VVIDEOEN | VAUDIOEN  | VSDEN;
329         pmic_reg_write(p, REG_MODE_1, val);
331         mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
332         gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
334         udelay(500);
336         gpio_set_value(IMX_GPIO_NR(2, 14), 1);
339 #ifdef CONFIG_FSL_ESDHC
340 int board_mmc_getcd(struct mmc *mmc)
342         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
343         int ret;
345         mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
346         gpio_direction_input(IMX_GPIO_NR(1, 0));
347         mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
348         gpio_direction_input(IMX_GPIO_NR(1, 6));
350         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
351                 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
352         else
353                 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
355         return ret;
358 int board_mmc_init(bd_t *bis)
360         u32 index;
361         s32 status = 0;
363         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
364         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
366         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
367                         index++) {
368                 switch (index) {
369                 case 0:
370                         mxc_request_iomux(MX51_PIN_SD1_CMD,
371                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
372                         mxc_request_iomux(MX51_PIN_SD1_CLK,
373                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
374                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
375                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
376                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
377                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
378                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
379                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
380                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
381                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
382                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
383                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
384                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
385                                 PAD_CTL_PUE_PULL |
386                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
387                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
388                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
389                                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
390                                 PAD_CTL_PUE_PULL |
391                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
392                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
393                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
394                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
395                                 PAD_CTL_PUE_PULL |
396                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
397                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
398                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
399                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
400                                 PAD_CTL_PUE_PULL |
401                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
402                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
403                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
404                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
405                                 PAD_CTL_PUE_PULL |
406                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
407                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
408                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
409                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
410                                 PAD_CTL_PUE_PULL |
411                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
412                         mxc_request_iomux(MX51_PIN_GPIO1_0,
413                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
414                         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
415                                 PAD_CTL_HYS_ENABLE);
416                         mxc_request_iomux(MX51_PIN_GPIO1_1,
417                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
418                         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
419                                 PAD_CTL_HYS_ENABLE);
420                         break;
421                 case 1:
422                         mxc_request_iomux(MX51_PIN_SD2_CMD,
423                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
424                         mxc_request_iomux(MX51_PIN_SD2_CLK,
425                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
426                         mxc_request_iomux(MX51_PIN_SD2_DATA0,
427                                 IOMUX_CONFIG_ALT0);
428                         mxc_request_iomux(MX51_PIN_SD2_DATA1,
429                                 IOMUX_CONFIG_ALT0);
430                         mxc_request_iomux(MX51_PIN_SD2_DATA2,
431                                 IOMUX_CONFIG_ALT0);
432                         mxc_request_iomux(MX51_PIN_SD2_DATA3,
433                                 IOMUX_CONFIG_ALT0);
434                         mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
435                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
436                                 PAD_CTL_SRE_FAST);
437                         mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
438                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
439                                 PAD_CTL_SRE_FAST);
440                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
441                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
442                                 PAD_CTL_SRE_FAST);
443                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
444                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
445                                 PAD_CTL_SRE_FAST);
446                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
447                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
448                                 PAD_CTL_SRE_FAST);
449                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
450                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
451                                 PAD_CTL_SRE_FAST);
452                         mxc_request_iomux(MX51_PIN_SD2_CMD,
453                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
454                         mxc_request_iomux(MX51_PIN_GPIO1_6,
455                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
456                         mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
457                                 PAD_CTL_HYS_ENABLE);
458                         mxc_request_iomux(MX51_PIN_GPIO1_5,
459                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
460                         mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
461                                 PAD_CTL_HYS_ENABLE);
462                         break;
463                 default:
464                         printf("Warning: you configured more ESDHC controller"
465                                 "(%d) as supported by the board(2)\n",
466                                 CONFIG_SYS_FSL_ESDHC_NUM);
467                         return status;
468                 }
469                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
470         }
471         return status;
473 #endif
475 int board_early_init_f(void)
477         setup_iomux_uart();
478         setup_iomux_fec();
479 #ifdef CONFIG_USB_EHCI_MX5
480         setup_usb_h1();
481 #endif
482         setup_iomux_lcd();
484         return 0;
487 int board_init(void)
489         /* address of boot parameters */
490         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
492         return 0;
495 #ifdef CONFIG_BOARD_LATE_INIT
496 int board_late_init(void)
498 #ifdef CONFIG_MXC_SPI
499         setup_iomux_spi();
500         power_init();
501 #endif
503         return 0;
505 #endif
507 /*
508  * Do not overwrite the console
509  * Use always serial for U-Boot console
510  */
511 int overwrite_console(void)
513         return 1;
516 int checkboard(void)
518         puts("Board: MX51EVK\n");
520         return 0;