board/freescale/mx51evk/mx51evk.c

   1 /*
   2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/gpio.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/mx5x_pins.h>
  28 #include <asm/arch/iomux.h>
  29 #include <asm/errno.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <asm/arch/crm_regs.h>
  32 #include <i2c.h>
  33 #include <mmc.h>
  34 #include <fsl_esdhc.h>
  35 #include <pmic.h>
  36 #include <fsl_pmic.h>
  37 #include <mc13892.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #ifdef CONFIG_FSL_ESDHC
  42 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  43         {MMC_SDHC1_BASE_ADDR, 1},
  44         {MMC_SDHC2_BASE_ADDR, 1},
  45 };
  46 #endif
  47
  48 int dram_init(void)
  49 {
  50         /* dram_init must store complete ramsize in gd->ram_size */
  51         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  52                                 PHYS_SDRAM_1_SIZE);
  53         return 0;
  54 }
  55
  56 static void setup_iomux_uart(void)
  57 {
  58         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
  59                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
  60
  61         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
  62         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
  63         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
  64         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
  65         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
  66         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
  67         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
  68         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
  69 }
  70
  71 static void setup_iomux_fec(void)
  72 {
  73         /*FEC_MDIO*/
  74         mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
  75         mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
  76
  77         /*FEC_MDC*/
  78         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
  79         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
  80
  81         /* FEC RDATA[3] */
  82         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
  83         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
  84
  85         /* FEC RDATA[2] */
  86         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
  87         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
  88
  89         /* FEC RDATA[1] */
  90         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
  91         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
  92
  93         /* FEC RDATA[0] */
  94         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
  95         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
  96
  97         /* FEC TDATA[3] */
  98         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
  99         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
 100
 101         /* FEC TDATA[2] */
 102         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
 103         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
 104
 105         /* FEC TDATA[1] */
 106         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
 107         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
 108
 109         /* FEC TDATA[0] */
 110         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
 111         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
 112
 113         /* FEC TX_EN */
 114         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
 115         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
 116
 117         /* FEC TX_ER */
 118         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
 119         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
 120
 121         /* FEC TX_CLK */
 122         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
 123         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
 124
 125         /* FEC TX_COL */
 126         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 127         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 128
 129         /* FEC RX_CLK */
 130         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 131         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 132
 133         /* FEC RX_CRS */
 134         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
 135         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
 136
 137         /* FEC RX_ER */
 138         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 139         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 140
 141         /* FEC RX_DV */
 142         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
 143         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
 144 }
 145
 146 #ifdef CONFIG_MXC_SPI
 147 static void setup_iomux_spi(void)
 148 {
 149         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 150         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 151         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
 152
 153         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 154         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 155         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
 156
 157         /* de-select SS1 of instance: ecspi1. */
 158         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 159         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
 160
 161         /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
 162         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 163         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
 164
 165         /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
 166         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
 167         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
 168
 169         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 170         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 171         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
 172 }
 173 #endif
 174
 175 static void power_init(void)
 176 {
 177         unsigned int val;
 178         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 179         struct pmic *p;
 180
 181         pmic_init();
 182         p = get_pmic();
 183
 184         /* Write needed to Power Gate 2 register */
 185         pmic_reg_read(p, REG_POWER_MISC, &val);
 186         val &= ~PWGT2SPIEN;
 187         pmic_reg_write(p, REG_POWER_MISC, val);
 188
 189         /* Externally powered */
 190         pmic_reg_read(p, REG_CHARGE, &val);
 191         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
 192         pmic_reg_write(p, REG_CHARGE, val);
 193
 194         /* power up the system first */
 195         pmic_reg_write(p, REG_POWER_MISC, PWUP);
 196
 197         /* Set core voltage to 1.1V */
 198         pmic_reg_read(p, REG_SW_0, &val);
 199         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
 200         pmic_reg_write(p, REG_SW_0, val);
 201
 202         /* Setup VCC (SW2) to 1.25 */
 203         pmic_reg_read(p, REG_SW_1, &val);
 204         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 205         pmic_reg_write(p, REG_SW_1, val);
 206
 207         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 208         pmic_reg_read(p, REG_SW_2, &val);
 209         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 210         pmic_reg_write(p, REG_SW_2, val);
 211         udelay(50);
 212
 213         /* Raise the core frequency to 800MHz */
 214         writel(0x0, &mxc_ccm->cacrr);
 215
 216         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 217         /* Setup the switcher mode for SW1 & SW2*/
 218         pmic_reg_read(p, REG_SW_4, &val);
 219         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 220                 (SWMODE_MASK << SWMODE2_SHIFT)));
 221         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 222                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 223         pmic_reg_write(p, REG_SW_4, val);
 224
 225         /* Setup the switcher mode for SW3 & SW4 */
 226         pmic_reg_read(p, REG_SW_5, &val);
 227         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 228                 (SWMODE_MASK << SWMODE4_SHIFT)));
 229         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 230                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 231         pmic_reg_write(p, REG_SW_5, val);
 232
 233         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
 234         pmic_reg_read(p, REG_SETTING_0, &val);
 235         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 236         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
 237         pmic_reg_write(p, REG_SETTING_0, val);
 238
 239         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 240         pmic_reg_read(p, REG_SETTING_1, &val);
 241         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 242         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
 243         pmic_reg_write(p, REG_SETTING_1, val);
 244
 245         /* Configure VGEN3 and VCAM regulators to use external PNP */
 246         val = VGEN3CONFIG | VCAMCONFIG;
 247         pmic_reg_write(p, REG_MODE_1, val);
 248         udelay(200);
 249
 250         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 251         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 252                 VVIDEOEN | VAUDIOEN  | VSDEN;
 253         pmic_reg_write(p, REG_MODE_1, val);
 254
 255         mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
 256         gpio_direction_output(46, 0);
 257
 258         udelay(500);
 259
 260         gpio_set_value(46, 1);
 261 }
 262
 263 #ifdef CONFIG_FSL_ESDHC
 264 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 265 {
 266         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 267
 268         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 269                 *cd = gpio_get_value(0);
 270         else
 271                 *cd = gpio_get_value(6);
 272
 273         return 0;
 274 }
 275
 276 int board_mmc_init(bd_t *bis)
 277 {
 278         u32 index;
 279         s32 status = 0;
 280
 281         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 282                         index++) {
 283                 switch (index) {
 284                 case 0:
 285                         mxc_request_iomux(MX51_PIN_SD1_CMD,
 286                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 287                         mxc_request_iomux(MX51_PIN_SD1_CLK,
 288                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 289                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 290                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 291                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 292                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 293                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 294                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 295                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 296                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 297                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 298                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 299                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 300                                 PAD_CTL_PUE_PULL |
 301                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 302                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 303                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 304                                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 305                                 PAD_CTL_PUE_PULL |
 306                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 307                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 308                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 309                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 310                                 PAD_CTL_PUE_PULL |
 311                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 312                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 313                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 314                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 315                                 PAD_CTL_PUE_PULL |
 316                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 317                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 318                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 319                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 320                                 PAD_CTL_PUE_PULL |
 321                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 322                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 323                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 324                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 325                                 PAD_CTL_PUE_PULL |
 326                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 327                         mxc_request_iomux(MX51_PIN_GPIO1_0,
 328                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 329                         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 330                                 PAD_CTL_HYS_ENABLE);
 331                         mxc_request_iomux(MX51_PIN_GPIO1_1,
 332                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 333                         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 334                                 PAD_CTL_HYS_ENABLE);
 335                         break;
 336                 case 1:
 337                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 338                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 339                         mxc_request_iomux(MX51_PIN_SD2_CLK,
 340                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 341                         mxc_request_iomux(MX51_PIN_SD2_DATA0,
 342                                 IOMUX_CONFIG_ALT0);
 343                         mxc_request_iomux(MX51_PIN_SD2_DATA1,
 344                                 IOMUX_CONFIG_ALT0);
 345                         mxc_request_iomux(MX51_PIN_SD2_DATA2,
 346                                 IOMUX_CONFIG_ALT0);
 347                         mxc_request_iomux(MX51_PIN_SD2_DATA3,
 348                                 IOMUX_CONFIG_ALT0);
 349                         mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
 350                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 351                                 PAD_CTL_SRE_FAST);
 352                         mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
 353                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 354                                 PAD_CTL_SRE_FAST);
 355                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
 356                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 357                                 PAD_CTL_SRE_FAST);
 358                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
 359                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 360                                 PAD_CTL_SRE_FAST);
 361                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
 362                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 363                                 PAD_CTL_SRE_FAST);
 364                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
 365                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 366                                 PAD_CTL_SRE_FAST);
 367                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 368                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 369                         mxc_request_iomux(MX51_PIN_GPIO1_6,
 370                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 371                         mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
 372                                 PAD_CTL_HYS_ENABLE);
 373                         mxc_request_iomux(MX51_PIN_GPIO1_5,
 374                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 375                         mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
 376                                 PAD_CTL_HYS_ENABLE);
 377                         break;
 378                 default:
 379                         printf("Warning: you configured more ESDHC controller"
 380                                 "(%d) as supported by the board(2)\n",
 381                                 CONFIG_SYS_FSL_ESDHC_NUM);
 382                         return status;
 383                 }
 384                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 385         }
 386         return status;
 387 }
 388 #endif
 389
 390 int board_early_init_f(void)
 391 {
 392         setup_iomux_uart();
 393         setup_iomux_fec();
 394
 395         return 0;
 396 }
 397
 398 int board_init(void)
 399 {
 400         /* address of boot parameters */
 401         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 402
 403         return 0;
 404 }
 405
 406 #ifdef CONFIG_BOARD_LATE_INIT
 407 int board_late_init(void)
 408 {
 409 #ifdef CONFIG_MXC_SPI
 410         setup_iomux_spi();
 411         power_init();
 412 #endif
 413         return 0;
 414 }
 415 #endif
 416
 417 int checkboard(void)
 418 {
 419         puts("Board: MX51EVK\n");
 420
 421         return 0;
 422 }