board/freescale/mx51evk/mx51evk.c

   1 /*
   2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/iomux.h>
  28 #include <asm/errno.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <i2c.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc.h>
  34 #include <fsl_pmic.h>
  35 #include <mc13892.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 static u32 system_rev;
  40
  41 #ifdef CONFIG_FSL_ESDHC
  42 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  43         {MMC_SDHC1_BASE_ADDR, 1},
  44         {MMC_SDHC2_BASE_ADDR, 1},
  45 };
  46 #endif
  47
  48 u32 get_board_rev(void)
  49 {
  50         return system_rev;
  51 }
  52
  53 int dram_init(void)
  54 {
  55         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  56         gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
  57                         PHYS_SDRAM_1_SIZE);
  58         return 0;
  59 }
  60
  61 static void setup_iomux_uart(void)
  62 {
  63         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
  64                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
  65
  66         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
  67         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
  68         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
  69         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
  70         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
  71         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
  72         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
  73         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
  74 }
  75
  76 static void setup_iomux_fec(void)
  77 {
  78         /*FEC_MDIO*/
  79         mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
  80         mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
  81
  82         /*FEC_MDC*/
  83         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
  84         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
  85
  86         /* FEC RDATA[3] */
  87         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
  88         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
  89
  90         /* FEC RDATA[2] */
  91         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
  92         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
  93
  94         /* FEC RDATA[1] */
  95         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
  96         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
  97
  98         /* FEC RDATA[0] */
  99         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 100         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 101
 102         /* FEC TDATA[3] */
 103         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
 104         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
 105
 106         /* FEC TDATA[2] */
 107         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
 108         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
 109
 110         /* FEC TDATA[1] */
 111         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
 112         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
 113
 114         /* FEC TDATA[0] */
 115         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
 116         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
 117
 118         /* FEC TX_EN */
 119         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
 120         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
 121
 122         /* FEC TX_ER */
 123         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
 124         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
 125
 126         /* FEC TX_CLK */
 127         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
 128         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
 129
 130         /* FEC TX_COL */
 131         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 132         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 133
 134         /* FEC RX_CLK */
 135         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 136         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 137
 138         /* FEC RX_CRS */
 139         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
 140         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
 141
 142         /* FEC RX_ER */
 143         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 144         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 145
 146         /* FEC RX_DV */
 147         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
 148         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
 149 }
 150
 151 #ifdef CONFIG_MXC_SPI
 152 static void setup_iomux_spi(void)
 153 {
 154         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 155         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 156         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
 157
 158         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 159         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 160         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
 161
 162         /* de-select SS1 of instance: ecspi1. */
 163         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 164         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
 165
 166         /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
 167         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 168         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
 169
 170         /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
 171         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
 172         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
 173
 174         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 175         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 176         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
 177 }
 178 #endif
 179
 180 static void power_init(void)
 181 {
 182         unsigned int val;
 183         unsigned int reg;
 184         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 185
 186         /* Write needed to Power Gate 2 register */
 187         val = pmic_reg_read(REG_POWER_MISC);
 188         val &= ~PWGT2SPIEN;
 189         pmic_reg_write(REG_POWER_MISC, val);
 190
 191         /* Write needed to update Charger 0 */
 192         pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
 193                 ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
 194                 OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
 195
 196         /* power up the system first */
 197         pmic_reg_write(REG_POWER_MISC, PWUP);
 198
 199         /* Set core voltage to 1.1V */
 200         val = pmic_reg_read(REG_SW_0);
 201         val = (val & (~0x1F)) | 0x14;
 202         pmic_reg_write(REG_SW_0, val);
 203
 204         /* Setup VCC (SW2) to 1.25 */
 205         val = pmic_reg_read(REG_SW_1);
 206         val = (val & (~0x1F)) | 0x1A;
 207         pmic_reg_write(REG_SW_1, val);
 208
 209         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 210         val = pmic_reg_read(REG_SW_2);
 211         val = (val & (~0x1F)) | 0x1A;
 212         pmic_reg_write(REG_SW_2, val);
 213         udelay(50);
 214
 215         /* Raise the core frequency to 800MHz */
 216         writel(0x0, &mxc_ccm->cacrr);
 217
 218         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 219         /* Setup the switcher mode for SW1 & SW2*/
 220         val = pmic_reg_read(REG_SW_4);
 221         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 222                 (SWMODE_MASK << SWMODE2_SHIFT)));
 223         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 224                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 225         pmic_reg_write(REG_SW_4, val);
 226
 227         /* Setup the switcher mode for SW3 & SW4 */
 228         val = pmic_reg_read(REG_SW_5);
 229         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 230                 (SWMODE_MASK << SWMODE4_SHIFT)));
 231         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 232                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 233         pmic_reg_write(REG_SW_5, val);
 234
 235         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
 236         val = pmic_reg_read(REG_SETTING_0);
 237         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 238         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
 239         pmic_reg_write(REG_SETTING_0, val);
 240
 241         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 242         val = pmic_reg_read(REG_SETTING_1);
 243         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 244         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
 245         pmic_reg_write(REG_SETTING_1, val);
 246
 247         /* Configure VGEN3 and VCAM regulators to use external PNP */
 248         val = VGEN3CONFIG | VCAMCONFIG;
 249         pmic_reg_write(REG_MODE_1, val);
 250         udelay(200);
 251
 252         reg = readl(GPIO2_BASE_ADDR + 0x0);
 253         reg &= ~0x4000;  /* Lower reset line */
 254         writel(reg, GPIO2_BASE_ADDR + 0x0);
 255
 256         reg = readl(GPIO2_BASE_ADDR + 0x4);
 257         reg |= 0x4000;  /* configure GPIO lines as output */
 258         writel(reg, GPIO2_BASE_ADDR + 0x4);
 259
 260         /* Reset the ethernet controller over GPIO */
 261         writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
 262
 263         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 264         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 265                 VVIDEOEN | VAUDIOEN  | VSDEN;
 266         pmic_reg_write(REG_MODE_1, val);
 267
 268         udelay(500);
 269
 270         reg = readl(GPIO2_BASE_ADDR + 0x0);
 271         reg |= 0x4000;
 272         writel(reg, GPIO2_BASE_ADDR + 0x0);
 273 }
 274
 275 #ifdef CONFIG_FSL_ESDHC
 276 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 277 {
 278         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 279
 280         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 281                 *cd = readl(GPIO1_BASE_ADDR) & 0x01;
 282         else
 283                 *cd = readl(GPIO1_BASE_ADDR) & 0x40;
 284
 285         return 0;
 286 }
 287
 288 int board_mmc_init(bd_t *bis)
 289 {
 290         u32 index;
 291         s32 status = 0;
 292
 293         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 294                         index++) {
 295                 switch (index) {
 296                 case 0:
 297                         mxc_request_iomux(MX51_PIN_SD1_CMD,
 298                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 299                         mxc_request_iomux(MX51_PIN_SD1_CLK,
 300                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 301                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 302                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 303                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 304                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 305                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 306                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 307                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 308                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 309                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 310                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 311                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 312                                 PAD_CTL_PUE_PULL |
 313                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 314                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 315                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 316                                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 317                                 PAD_CTL_PUE_PULL |
 318                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 319                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 320                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 321                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 322                                 PAD_CTL_PUE_PULL |
 323                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 324                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 325                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 326                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 327                                 PAD_CTL_PUE_PULL |
 328                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 329                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 330                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 331                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 332                                 PAD_CTL_PUE_PULL |
 333                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 334                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 335                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 336                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 337                                 PAD_CTL_PUE_PULL |
 338                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 339                         mxc_request_iomux(MX51_PIN_GPIO1_0,
 340                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 341                         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 342                                 PAD_CTL_HYS_ENABLE);
 343                         mxc_request_iomux(MX51_PIN_GPIO1_1,
 344                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 345                         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 346                                 PAD_CTL_HYS_ENABLE);
 347                         break;
 348                 case 1:
 349                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 350                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 351                         mxc_request_iomux(MX51_PIN_SD2_CLK,
 352                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 353                         mxc_request_iomux(MX51_PIN_SD2_DATA0,
 354                                 IOMUX_CONFIG_ALT0);
 355                         mxc_request_iomux(MX51_PIN_SD2_DATA1,
 356                                 IOMUX_CONFIG_ALT0);
 357                         mxc_request_iomux(MX51_PIN_SD2_DATA2,
 358                                 IOMUX_CONFIG_ALT0);
 359                         mxc_request_iomux(MX51_PIN_SD2_DATA3,
 360                                 IOMUX_CONFIG_ALT0);
 361                         mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
 362                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 363                                 PAD_CTL_SRE_FAST);
 364                         mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
 365                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 366                                 PAD_CTL_SRE_FAST);
 367                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
 368                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 369                                 PAD_CTL_SRE_FAST);
 370                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
 371                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 372                                 PAD_CTL_SRE_FAST);
 373                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
 374                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 375                                 PAD_CTL_SRE_FAST);
 376                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
 377                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 378                                 PAD_CTL_SRE_FAST);
 379                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 380                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 381                         mxc_request_iomux(MX51_PIN_GPIO1_6,
 382                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 383                         mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
 384                                 PAD_CTL_HYS_ENABLE);
 385                         mxc_request_iomux(MX51_PIN_GPIO1_5,
 386                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 387                         mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
 388                                 PAD_CTL_HYS_ENABLE);
 389                         break;
 390                 default:
 391                         printf("Warning: you configured more ESDHC controller"
 392                                 "(%d) as supported by the board(2)\n",
 393                                 CONFIG_SYS_FSL_ESDHC_NUM);
 394                         return status;
 395                 }
 396                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 397         }
 398         return status;
 399 }
 400 #endif
 401
 402 int board_init(void)
 403 {
 404         system_rev = get_cpu_rev();
 405
 406         gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
 407         /* address of boot parameters */
 408         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 409
 410         setup_iomux_uart();
 411         setup_iomux_fec();
 412
 413         return 0;
 414 }
 415
 416 #ifdef BOARD_LATE_INIT
 417 int board_late_init(void)
 418 {
 419 #ifdef CONFIG_MXC_SPI
 420         setup_iomux_spi();
 421         power_init();
 422 #endif
 423         return 0;
 424 }
 425 #endif
 426
 427 int checkboard(void)
 428 {
 429         puts("Board: MX51EVK ");
 430
 431         switch (system_rev & 0xff) {
 432         case CHIP_REV_3_0:
 433                 puts("3.0 [");
 434                 break;
 435         case CHIP_REV_2_5:
 436                 puts("2.5 [");
 437                 break;
 438         case CHIP_REV_2_0:
 439                 puts("2.0 [");
 440                 break;
 441         case CHIP_REV_1_1:
 442                 puts("1.1 [");
 443                 break;
 444         case CHIP_REV_1_0:
 445         default:
 446                 puts("1.0 [");
 447                 break;
 448         }
 449
 450         switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
 451         case 0x0001:
 452                 puts("POR");
 453                 break;
 454         case 0x0009:
 455                 puts("RST");
 456                 break;
 457         case 0x0010:
 458         case 0x0011:
 459                 puts("WDOG");
 460                 break;
 461         default:
 462                 puts("unknown");
 463         }
 464         puts("]\n");
 465         return 0;
 466 }