1 /*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 #include <common.h>
25 #include <asm/io.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/iomux.h>
32 #include <asm/arch/clock.h>
33 #include <asm/errno.h>
34 #include <asm/imx-common/mx5_video.h>
35 #include <netdev.h>
36 #include <i2c.h>
37 #include <mmc.h>
38 #include <fsl_esdhc.h>
39 #include <asm/gpio.h>
40 #include <power/pmic.h>
41 #include <dialog_pmic.h>
42 #include <fsl_pmic.h>
43 #include <linux/fb.h>
44 #include <ipu_pixfmt.h>
46 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
48 DECLARE_GLOBAL_DATA_PTR;
50 int dram_init(void)
51 {
52 u32 size1, size2;
54 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
55 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
57 gd->ram_size = size1 + size2;
59 return 0;
60 }
61 void dram_init_banksize(void)
62 {
63 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
64 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
66 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
67 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
68 }
70 u32 get_board_rev(void)
71 {
72 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
73 struct fuse_bank *bank = &iim->bank[0];
74 struct fuse_bank0_regs *fuse =
75 (struct fuse_bank0_regs *)bank->fuse_regs;
77 int rev = readl(&fuse->gp[6]);
79 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
80 rev = 0;
82 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
83 }
85 static void setup_iomux_uart(void)
86 {
87 /* UART1 RXD */
88 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
89 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
90 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
91 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
92 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
93 PAD_CTL_ODE_OPENDRAIN_ENABLE);
94 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
96 /* UART1 TXD */
97 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
98 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
99 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
100 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
101 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
102 PAD_CTL_ODE_OPENDRAIN_ENABLE);
103 }
105 #ifdef CONFIG_USB_EHCI_MX5
106 int board_ehci_hcd_init(int port)
107 {
108 /* request VBUS power enable pin, GPIO7_8 */
109 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
110 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
111 return 0;
112 }
113 #endif
115 static void setup_iomux_fec(void)
116 {
117 /*FEC_MDIO*/
118 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
119 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
120 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
121 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
122 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
123 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
125 /*FEC_MDC*/
126 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
127 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
129 /* FEC RXD1 */
130 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
131 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
132 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
134 /* FEC RXD0 */
135 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
136 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
137 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
139 /* FEC TXD1 */
140 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
141 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
143 /* FEC TXD0 */
144 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
145 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
147 /* FEC TX_EN */
148 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
149 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
151 /* FEC TX_CLK */
152 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
153 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
154 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
156 /* FEC RX_ER */
157 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
158 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
159 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
161 /* FEC CRS */
162 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
163 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
164 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
165 }
167 #ifdef CONFIG_FSL_ESDHC
168 struct fsl_esdhc_cfg esdhc_cfg[2] = {
169 {MMC_SDHC1_BASE_ADDR},
170 {MMC_SDHC3_BASE_ADDR},
171 };
173 int board_mmc_getcd(struct mmc *mmc)
174 {
175 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
176 int ret;
178 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
179 gpio_direction_input(IMX_GPIO_NR(3, 11));
180 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
181 gpio_direction_input(IMX_GPIO_NR(3, 13));
183 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
184 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
185 else
186 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
188 return ret;
189 }
191 int board_mmc_init(bd_t *bis)
192 {
193 u32 index;
194 s32 status = 0;
196 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
197 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
199 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
200 switch (index) {
201 case 0:
202 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
203 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
204 mxc_request_iomux(MX53_PIN_SD1_DATA0,
205 IOMUX_CONFIG_ALT0);
206 mxc_request_iomux(MX53_PIN_SD1_DATA1,
207 IOMUX_CONFIG_ALT0);
208 mxc_request_iomux(MX53_PIN_SD1_DATA2,
209 IOMUX_CONFIG_ALT0);
210 mxc_request_iomux(MX53_PIN_SD1_DATA3,
211 IOMUX_CONFIG_ALT0);
212 mxc_request_iomux(MX53_PIN_EIM_DA13,
213 IOMUX_CONFIG_ALT1);
215 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
216 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
217 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
218 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
219 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
220 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
221 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
222 PAD_CTL_DRV_HIGH);
223 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
224 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
225 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
226 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
227 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
228 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
229 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
230 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
231 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
232 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
233 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
234 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
235 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
236 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
237 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
238 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
239 break;
240 case 1:
241 mxc_request_iomux(MX53_PIN_ATA_RESET_B,
242 IOMUX_CONFIG_ALT2);
243 mxc_request_iomux(MX53_PIN_ATA_IORDY,
244 IOMUX_CONFIG_ALT2);
245 mxc_request_iomux(MX53_PIN_ATA_DATA8,
246 IOMUX_CONFIG_ALT4);
247 mxc_request_iomux(MX53_PIN_ATA_DATA9,
248 IOMUX_CONFIG_ALT4);
249 mxc_request_iomux(MX53_PIN_ATA_DATA10,
250 IOMUX_CONFIG_ALT4);
251 mxc_request_iomux(MX53_PIN_ATA_DATA11,
252 IOMUX_CONFIG_ALT4);
253 mxc_request_iomux(MX53_PIN_ATA_DATA0,
254 IOMUX_CONFIG_ALT4);
255 mxc_request_iomux(MX53_PIN_ATA_DATA1,
256 IOMUX_CONFIG_ALT4);
257 mxc_request_iomux(MX53_PIN_ATA_DATA2,
258 IOMUX_CONFIG_ALT4);
259 mxc_request_iomux(MX53_PIN_ATA_DATA3,
260 IOMUX_CONFIG_ALT4);
261 mxc_request_iomux(MX53_PIN_EIM_DA11,
262 IOMUX_CONFIG_ALT1);
264 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
265 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
266 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
267 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
268 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
269 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
270 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
271 PAD_CTL_DRV_HIGH);
272 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
273 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
274 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
275 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
276 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
277 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
278 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
279 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
280 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
281 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
282 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
283 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
284 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
285 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
286 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
287 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
288 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
289 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
290 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
291 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
292 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
293 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
294 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
295 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
296 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
297 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
298 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
299 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
300 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
301 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
302 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
303 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
305 break;
306 default:
307 printf("Warning: you configured more ESDHC controller"
308 "(%d) as supported by the board(2)\n",
309 CONFIG_SYS_FSL_ESDHC_NUM);
310 return status;
311 }
312 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
313 }
315 return status;
316 }
317 #endif
319 static void setup_iomux_i2c(void)
320 {
321 /* I2C1 SDA */
322 mxc_request_iomux(MX53_PIN_CSI0_D8,
323 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
324 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
325 INPUT_CTL_PATH0);
326 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
327 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
328 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
329 PAD_CTL_PUE_PULL |
330 PAD_CTL_ODE_OPENDRAIN_ENABLE);
331 /* I2C1 SCL */
332 mxc_request_iomux(MX53_PIN_CSI0_D9,
333 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
334 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
335 INPUT_CTL_PATH0);
336 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
337 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
338 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
339 PAD_CTL_PUE_PULL |
340 PAD_CTL_ODE_OPENDRAIN_ENABLE);
341 }
343 static int power_init(void)
344 {
345 unsigned int val;
346 int ret;
347 struct pmic *p;
349 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
350 ret = pmic_dialog_init(I2C_PMIC);
351 if (ret)
352 return ret;
354 p = pmic_get("DIALOG_PMIC");
355 if (!p)
356 return -ENODEV;
358 /* Set VDDA to 1.25V */
359 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
360 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
361 if (ret) {
362 printf("Writing to BUCKCORE_REG failed: %d\n", ret);
363 return ret;
364 }
366 pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
367 val |= DA9052_SUPPLY_VBCOREGO;
368 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
369 if (ret) {
370 printf("Writing to SUPPLY_REG failed: %d\n", ret);
371 return ret;
372 }
374 /* Set Vcc peripheral to 1.30V */
375 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
376 if (ret) {
377 printf("Writing to BUCKPRO_REG failed: %d\n", ret);
378 return ret;
379 }
381 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
382 if (ret) {
383 printf("Writing to SUPPLY_REG failed: %d\n", ret);
384 return ret;
385 }
387 return ret;
388 }
390 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
391 ret = pmic_init(I2C_PMIC);
392 if (ret)
393 return ret;
395 p = pmic_get("FSL_PMIC");
396 if (!p)
397 return -ENODEV;
399 /* Set VDDGP to 1.25V for 1GHz on SW1 */
400 pmic_reg_read(p, REG_SW_0, &val);
401 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
402 ret = pmic_reg_write(p, REG_SW_0, val);
403 if (ret) {
404 printf("Writing to REG_SW_0 failed: %d\n", ret);
405 return ret;
406 }
408 /* Set VCC as 1.30V on SW2 */
409 pmic_reg_read(p, REG_SW_1, &val);
410 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
411 ret = pmic_reg_write(p, REG_SW_1, val);
412 if (ret) {
413 printf("Writing to REG_SW_1 failed: %d\n", ret);
414 return ret;
415 }
417 /* Set global reset timer to 4s */
418 pmic_reg_read(p, REG_POWER_CTL2, &val);
419 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
420 ret = pmic_reg_write(p, REG_POWER_CTL2, val);
421 if (ret) {
422 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
423 return ret;
424 }
426 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
427 pmic_reg_read(p, REG_MODE_0, &val);
428 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
429 ret = pmic_reg_write(p, REG_MODE_0, val);
430 if (ret) {
431 printf("Writing to REG_MODE_0 failed: %d\n", ret);
432 return ret;
433 }
435 /* Set SWBST to 5V in auto mode */
436 val = SWBST_AUTO;
437 ret = pmic_reg_write(p, SWBST_CTRL, val);
438 if (ret) {
439 printf("Writing to SWBST_CTRL failed: %d\n", ret);
440 return ret;
441 }
443 return ret;
444 }
446 return -1;
447 }
449 static void clock_1GHz(void)
450 {
451 int ret;
452 u32 ref_clk = MXC_HCLK;
453 /*
454 * After increasing voltage to 1.25V, we can switch
455 * CPU clock to 1GHz and DDR to 400MHz safely
456 */
457 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
458 if (ret)
459 printf("CPU: Switch CPU clock to 1GHZ failed\n");
461 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
462 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
463 if (ret)
464 printf("CPU: Switch DDR clock to 400MHz failed\n");
465 }
467 int board_early_init_f(void)
468 {
469 setup_iomux_uart();
470 setup_iomux_fec();
471 setup_iomux_lcd();
473 return 0;
474 }
476 int print_cpuinfo(void)
477 {
478 u32 cpurev;
480 cpurev = get_cpu_rev();
481 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
482 (cpurev & 0xFF000) >> 12,
483 (cpurev & 0x000F0) >> 4,
484 (cpurev & 0x0000F) >> 0,
485 mxc_get_clock(MXC_ARM_CLK) / 1000000);
486 printf("Reset cause: %s\n", get_reset_cause());
487 return 0;
488 }
490 /*
491 * Do not overwrite the console
492 * Use always serial for U-Boot console
493 */
494 int overwrite_console(void)
495 {
496 return 1;
497 }
499 int board_init(void)
500 {
501 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
503 mxc_set_sata_internal_clock();
504 setup_iomux_i2c();
506 lcd_enable();
508 return 0;
509 }
511 int board_late_init(void)
512 {
513 if (!power_init())
514 clock_1GHz();
515 print_cpuinfo();
517 return 0;
518 }
520 int checkboard(void)
521 {
522 puts("Board: MX53 LOCO\n");
524 return 0;
525 }