1 /*
2 * Copyright (C) 2009 Pegatron Corporation
3 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
4 * Copyright (C) 2009-2012 Genesi USA, Inc.
5 *
6 * BASED ON: imx51evk
7 *
8 * (C) Copyright 2009
9 * Stefano Babic DENX Software Engineering sbabic@denx.de.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not write to the Free Software
26 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
27 * MA 02110-1301 USA
28 *
29 * Refer docs/README.imxmage for more details about how-to configure
30 * and create imximage boot image
31 *
32 * The syntax is taken as close as possible with the kwbimage
33 */
35 /*
36 * Boot Device : one of
37 * spi, sd (the board has no nand neither onenand)
38 */
39 BOOT_FROM spi
41 /*
42 * Device Configuration Data (DCD)
43 *
44 * Each entry must have the format:
45 * Addr-type Address Value
46 *
47 * where:
48 * Addr-type register length (1,2 or 4 bytes)
49 * Address absolute address of the register
50 * value value to be stored in the register
51 */
52 /* DDR bus IOMUX PAD settings */
53 DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
54 DATA 4 0x73fa850c 0x20c5 # SDODT1
55 DATA 4 0x73fa8510 0x20c5 # SDODT0
56 DATA 4 0x73fa8848 0x4 # DDR_A1
57 DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
58 DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
59 DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
60 DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
61 DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
62 DATA 4 0x73fa8820 0x0 # DDRPKS
63 DATA 4 0x73fa84ac 0xe5 # SDWE
64 DATA 4 0x73fa84b0 0xe5 # SDCKE0
65 DATA 4 0x73fa84b4 0xe5 # SDCKE1
66 DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
67 DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
69 /*
70 * Setting DDR for micron
71 * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
72 * CAS=3 BL=4
73 */
74 /* ESDCTL_ESDCTL0 */
75 DATA 4 0x83fd9000 0x82a20000
76 /* ESDCTL_ESDCTL1 */
77 DATA 4 0x83fd9008 0x82a20000
78 /* ESDCTL_ESDMISC */
79 DATA 4 0x83fd9010 0xcaaaf6d0
80 /* ESDCTL_ESDCFG0 */
81 DATA 4 0x83fd9004 0x333574aa
82 /* ESDCTL_ESDCFG1 */
83 DATA 4 0x83fd900c 0x333574aa
85 /* Init DRAM on CS0 */
86 /* ESDCTL_ESDSCR */
87 DATA 4 0x83fd9014 0x04008008
88 DATA 4 0x83fd9014 0x0000801a
89 DATA 4 0x83fd9014 0x0000801b
90 DATA 4 0x83fd9014 0x00448019
91 DATA 4 0x83fd9014 0x07328018
92 DATA 4 0x83fd9014 0x04008008
93 DATA 4 0x83fd9014 0x00008010
94 DATA 4 0x83fd9014 0x00008010
95 DATA 4 0x83fd9014 0x06328018
96 DATA 4 0x83fd9014 0x03808019
97 DATA 4 0x83fd9014 0x00408019
98 DATA 4 0x83fd9014 0x00008000
100 /* Init DRAM on CS1 */
101 DATA 4 0x83fd9014 0x0400800c
102 DATA 4 0x83fd9014 0x0000801e
103 DATA 4 0x83fd9014 0x0000801f
104 DATA 4 0x83fd9014 0x0000801d
105 DATA 4 0x83fd9014 0x0732801c
106 DATA 4 0x83fd9014 0x0400800c
107 DATA 4 0x83fd9014 0x00008014
108 DATA 4 0x83fd9014 0x00008014
109 DATA 4 0x83fd9014 0x0632801c
110 DATA 4 0x83fd9014 0x0380801d
111 DATA 4 0x83fd9014 0x0042801d
112 DATA 4 0x83fd9014 0x00008004
114 /* Write to CTL0 */
115 DATA 4 0x83fd9000 0xb2a20000
116 /* Write to CTL1 */
117 DATA 4 0x83fd9008 0xb2a20000
118 /* ESDMISC */
119 DATA 4 0x83fd9010 0xcaaaf6d0
120 /* ESDCTL_ESDCDLYGD */
121 DATA 4 0x83fd9034 0x90000000
122 DATA 4 0x83fd9014 0x00000000