b371376bc72c0f6d0b5c6118057065a6cd1679e4
[glsdk/glsdk-u-boot.git] / board / ti / am335x / board.c
1 /*
2  * board.c
3  *
4  * Board functions for TI AM335X based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
19 #include <common.h>
20 #include <errno.h>
21 #include <spl.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/io.h>
31 #include <asm/emif.h>
32 #include <asm/gpio.h>
33 #include <i2c.h>
34 #include <miiphy.h>
35 #include <cpsw.h>
36 #include "board.h"
38 DECLARE_GLOBAL_DATA_PTR;
40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
41 #ifdef CONFIG_SPL_BUILD
42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
43 #endif
45 /* MII mode defines */
46 #define MII_MODE_ENABLE         0x0
47 #define RGMII_MODE_ENABLE       0x3A
49 /* GPIO that controls power to DDR on EVM-SK */
50 #define GPIO_DDR_VTT_EN         7
52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
54 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
56 static inline int board_is_bone(void)
57 {
58         return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
59 }
61 static inline int board_is_bone_lt(void)
62 {
63         return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
64 }
66 static inline int board_is_evm_sk(void)
67 {
68         return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
69 }
71 static inline int board_is_idk(void)
72 {
73         return !strncmp(header.config, "SKU#02", 6);
74 }
76 static int __maybe_unused board_is_gp_evm(void)
77 {
78         return !strncmp("A33515BB", header.name, 8);
79 }
81 int board_is_evm_15_or_later(void)
82 {
83         return (!strncmp("A33515BB", header.name, 8) &&
84                 strncmp("1.5", header.version, 3) <= 0);
85 }
87 /*
88  * Read header information from EEPROM into global structure.
89  */
90 static int read_eeprom(void)
91 {
92         /* Check if baseboard eeprom is available */
93         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
94                 puts("Could not probe the EEPROM; something fundamentally "
95                         "wrong on the I2C bus.\n");
96                 return -ENODEV;
97         }
99         /* read the eeprom using i2c */
100         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
101                                                         sizeof(header))) {
102                 puts("Could not read the EEPROM; something fundamentally"
103                         " wrong on the I2C bus.\n");
104                 return -EIO;
105         }
107         if (header.magic != 0xEE3355AA) {
108                 /*
109                  * read the eeprom using i2c again,
110                  * but use only a 1 byte address
111                  */
112                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
113                                         (uchar *)&header, sizeof(header))) {
114                         puts("Could not read the EEPROM; something "
115                                 "fundamentally wrong on the I2C bus.\n");
116                         return -EIO;
117                 }
119                 if (header.magic != 0xEE3355AA) {
120                         printf("Incorrect magic number (0x%x) in EEPROM\n",
121                                         header.magic);
122                         return -EINVAL;
123                 }
124         }
126         return 0;
129 /* UART Defines */
130 #ifdef CONFIG_SPL_BUILD
131 #define UART_RESET              (0x1 << 1)
132 #define UART_CLK_RUNNING_MASK   0x1
133 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
135 static void rtc32k_enable(void)
137         struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
139         /*
140          * Unlock the RTC's registers.  For more details please see the
141          * RTC_SS section of the TRM.  In order to unlock we need to
142          * write these specific values (keys) in this order.
143          */
144         writel(0x83e70b13, &rtc->kick0r);
145         writel(0x95a4f1e0, &rtc->kick1r);
147         /* Enable the RTC 32K OSC by setting bits 3 and 6. */
148         writel((1 << 3) | (1 << 6), &rtc->osc);
151 static const struct ddr_data ddr2_data = {
152         .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
153                           (MT47H128M16RT25E_RD_DQS<<20) |
154                           (MT47H128M16RT25E_RD_DQS<<10) |
155                           (MT47H128M16RT25E_RD_DQS<<0)),
156         .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
157                           (MT47H128M16RT25E_WR_DQS<<20) |
158                           (MT47H128M16RT25E_WR_DQS<<10) |
159                           (MT47H128M16RT25E_WR_DQS<<0)),
160         .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
161                          (MT47H128M16RT25E_PHY_WRLVL<<20) |
162                          (MT47H128M16RT25E_PHY_WRLVL<<10) |
163                          (MT47H128M16RT25E_PHY_WRLVL<<0)),
164         .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
165                          (MT47H128M16RT25E_PHY_GATELVL<<20) |
166                          (MT47H128M16RT25E_PHY_GATELVL<<10) |
167                          (MT47H128M16RT25E_PHY_GATELVL<<0)),
168         .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
169                           (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
170                           (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
171                           (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
172         .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
173                           (MT47H128M16RT25E_PHY_WR_DATA<<20) |
174                           (MT47H128M16RT25E_PHY_WR_DATA<<10) |
175                           (MT47H128M16RT25E_PHY_WR_DATA<<0)),
176         .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
177         .datadldiff0 = PHY_DLL_LOCK_DIFF,
178 };
180 static const struct cmd_control ddr2_cmd_ctrl_data = {
181         .cmd0csratio = MT47H128M16RT25E_RATIO,
182         .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
183         .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
185         .cmd1csratio = MT47H128M16RT25E_RATIO,
186         .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
187         .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
189         .cmd2csratio = MT47H128M16RT25E_RATIO,
190         .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
191         .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
192 };
194 static const struct emif_regs ddr2_emif_reg_data = {
195         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
196         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
197         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
198         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
199         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
200         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
201 };
203 static const struct ddr_data ddr3_data = {
204         .datardsratio0 = MT41J128MJT125_RD_DQS,
205         .datawdsratio0 = MT41J128MJT125_WR_DQS,
206         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
207         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
208         .datadldiff0 = PHY_DLL_LOCK_DIFF,
209 };
211 static const struct ddr_data ddr3_beagleblack_data = {
212         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
213         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
214         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
215         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
216         .datadldiff0 = PHY_DLL_LOCK_DIFF,
217 };
219 static const struct ddr_data ddr3_evm_data = {
220         .datardsratio0 = MT41J512M8RH125_RD_DQS,
221         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
222         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
223         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
224         .datadldiff0 = PHY_DLL_LOCK_DIFF,
225 };
227 static const struct cmd_control ddr3_cmd_ctrl_data = {
228         .cmd0csratio = MT41J128MJT125_RATIO,
229         .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
230         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
232         .cmd1csratio = MT41J128MJT125_RATIO,
233         .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
234         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
236         .cmd2csratio = MT41J128MJT125_RATIO,
237         .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
238         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
239 };
241 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
242         .cmd0csratio = MT41K256M16HA125E_RATIO,
243         .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
244         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
246         .cmd1csratio = MT41K256M16HA125E_RATIO,
247         .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
248         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
250         .cmd2csratio = MT41K256M16HA125E_RATIO,
251         .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
252         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
253 };
255 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
256         .cmd0csratio = MT41J512M8RH125_RATIO,
257         .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
258         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
260         .cmd1csratio = MT41J512M8RH125_RATIO,
261         .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
262         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
264         .cmd2csratio = MT41J512M8RH125_RATIO,
265         .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
266         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
267 };
269 static struct emif_regs ddr3_emif_reg_data = {
270         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
271         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
272         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
273         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
274         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
275         .zq_config = MT41J128MJT125_ZQ_CFG,
276         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
277                                 PHY_EN_DYN_PWRDN,
278 };
280 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
281         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
282         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
283         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
284         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
285         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
286         .zq_config = MT41K256M16HA125E_ZQ_CFG,
287         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
288 };
290 static struct emif_regs ddr3_evm_emif_reg_data = {
291         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
292         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
293         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
294         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
295         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
296         .zq_config = MT41J512M8RH125_ZQ_CFG,
297         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
298                                 PHY_EN_DYN_PWRDN,
299 };
300 #endif
302 /*
303  * early system init of muxing and clocks.
304  */
305 void s_init(void)
307         /* WDT1 is already running when the bootloader gets control
308          * Disable it to avoid "random" resets
309          */
310         writel(0xAAAA, &wdtimer->wdtwspr);
311         while (readl(&wdtimer->wdtwwps) != 0x0)
312                 ;
313         writel(0x5555, &wdtimer->wdtwspr);
314         while (readl(&wdtimer->wdtwwps) != 0x0)
315                 ;
317 #ifdef CONFIG_SPL_BUILD
318         /* Setup the PLLs and the clocks for the peripherals */
319         pll_init();
321         /* Enable RTC32K clock */
322         rtc32k_enable();
324         /* UART softreset */
325         u32 regVal;
327 #ifdef CONFIG_SERIAL1
328         enable_uart0_pin_mux();
329 #endif /* CONFIG_SERIAL1 */
330 #ifdef CONFIG_SERIAL2
331         enable_uart1_pin_mux();
332 #endif /* CONFIG_SERIAL2 */
333 #ifdef CONFIG_SERIAL3
334         enable_uart2_pin_mux();
335 #endif /* CONFIG_SERIAL3 */
336 #ifdef CONFIG_SERIAL4
337         enable_uart3_pin_mux();
338 #endif /* CONFIG_SERIAL4 */
339 #ifdef CONFIG_SERIAL5
340         enable_uart4_pin_mux();
341 #endif /* CONFIG_SERIAL5 */
342 #ifdef CONFIG_SERIAL6
343         enable_uart5_pin_mux();
344 #endif /* CONFIG_SERIAL6 */
346         regVal = readl(&uart_base->uartsyscfg);
347         regVal |= UART_RESET;
348         writel(regVal, &uart_base->uartsyscfg);
349         while ((readl(&uart_base->uartsyssts) &
350                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
351                 ;
353         /* Disable smart idle */
354         regVal = readl(&uart_base->uartsyscfg);
355         regVal |= UART_SMART_IDLE_EN;
356         writel(regVal, &uart_base->uartsyscfg);
358         gd = &gdata;
360         preloader_console_init();
362         /* Initalize the board header */
363         enable_i2c0_pin_mux();
364         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
365         if (read_eeprom() < 0)
366                 puts("Could not get board ID.\n");
368         enable_board_pin_mux(&header);
369         if (board_is_evm_sk()) {
370                 /*
371                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
372                  * This is safe enough to do on older revs.
373                  */
374                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
375                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
376         }
378         if (board_is_evm_sk())
379                 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
380                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
381         else if (board_is_bone_lt())
382                 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
383                            &ddr3_beagleblack_data,
384                            &ddr3_beagleblack_cmd_ctrl_data,
385                            &ddr3_beagleblack_emif_reg_data, 0);
386         else if (board_is_evm_15_or_later())
387                 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
388                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
389         else
390                 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
391                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
392 #endif
395 /*
396  * Basic board specific setup.  Pinmux has been handled already.
397  */
398 int board_init(void)
400         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
401         if (read_eeprom() < 0)
402                 puts("Could not get board ID.\n");
404         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
406         gpmc_init();
408         return 0;
411 #ifdef CONFIG_BOARD_LATE_INIT
412 int board_late_init(void)
414 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
415         char safe_string[HDR_NAME_LEN + 1];
417         /* Now set variables based on the header. */
418         strncpy(safe_string, (char *)header.name, sizeof(header.name));
419         safe_string[sizeof(header.name)] = 0;
420         setenv("board_name", safe_string);
422         strncpy(safe_string, (char *)header.version, sizeof(header.version));
423         safe_string[sizeof(header.version)] = 0;
424         setenv("board_rev", safe_string);
425 #endif
427         return 0;
429 #endif
431 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
432         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
433 static void cpsw_control(int enabled)
435         /* VTP can be added here */
437         return;
440 static struct cpsw_slave_data cpsw_slaves[] = {
441         {
442                 .slave_reg_ofs  = 0x208,
443                 .sliver_reg_ofs = 0xd80,
444                 .phy_id         = 0,
445         },
446         {
447                 .slave_reg_ofs  = 0x308,
448                 .sliver_reg_ofs = 0xdc0,
449                 .phy_id         = 1,
450         },
451 };
453 static struct cpsw_platform_data cpsw_data = {
454         .mdio_base              = CPSW_MDIO_BASE,
455         .cpsw_base              = CPSW_BASE,
456         .mdio_div               = 0xff,
457         .channels               = 8,
458         .cpdma_reg_ofs          = 0x800,
459         .slaves                 = 1,
460         .slave_data             = cpsw_slaves,
461         .ale_reg_ofs            = 0xd00,
462         .ale_entries            = 1024,
463         .host_port_reg_ofs      = 0x108,
464         .hw_stats_reg_ofs       = 0x900,
465         .mac_control            = (1 << 5),
466         .control                = cpsw_control,
467         .host_port_num          = 0,
468         .version                = CPSW_CTRL_VERSION_2,
469 };
470 #endif
472 #if defined(CONFIG_DRIVER_TI_CPSW) || \
473         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
474 int board_eth_init(bd_t *bis)
476         int rv, n = 0;
477         uint8_t mac_addr[6];
478         uint32_t mac_hi, mac_lo;
480         /* try reading mac address from efuse */
481         mac_lo = readl(&cdev->macid0l);
482         mac_hi = readl(&cdev->macid0h);
483         mac_addr[0] = mac_hi & 0xFF;
484         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
485         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
486         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
487         mac_addr[4] = mac_lo & 0xFF;
488         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
490 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
491         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
492         if (!getenv("ethaddr")) {
493                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
495                 if (is_valid_ether_addr(mac_addr))
496                         eth_setenv_enetaddr("ethaddr", mac_addr);
497         }
499         if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
500                 writel(MII_MODE_ENABLE, &cdev->miisel);
501                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
502                                 PHY_INTERFACE_MODE_MII;
503         } else {
504                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
505                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
506                                 PHY_INTERFACE_MODE_RGMII;
507         }
509         rv = cpsw_register(&cpsw_data);
510         if (rv < 0)
511                 printf("Error %d registering CPSW switch\n", rv);
512         else
513                 n += rv;
515         /*
516          *
517          * CPSW RGMII Internal Delay Mode is not supported in all PVT
518          * operating points.  So we must set the TX clock delay feature
519          * in the AR8051 PHY.  Since we only support a single ethernet
520          * device in U-Boot, we only do this for the first instance.
521          */
522 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
523 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
524 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
525 #define AR8051_RGMII_TX_CLK_DLY         0x100
527         if (board_is_evm_sk() || board_is_gp_evm()) {
528                 const char *devname;
529                 devname = miiphy_get_current_dev();
531                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
532                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
533                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
534                                 AR8051_RGMII_TX_CLK_DLY);
535         }
536 #endif
537 #if defined(CONFIG_USB_ETHER) && \
538         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
539         if (is_valid_ether_addr(mac_addr))
540                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
542         rv = usb_eth_initialize(bis);
543         if (rv < 0)
544                 printf("Error %d registering USB_ETHER\n", rv);
545         else
546                 n += rv;
547 #endif
548         return n;
550 #endif