1 /*
2 * board.c
3 *
4 * Board functions for TI AM335X based boards
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #include <common.h>
20 #include <errno.h>
21 #include <spl.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/io.h>
31 #include <asm/emif.h>
32 #include <asm/gpio.h>
33 #include <i2c.h>
34 #include <miiphy.h>
35 #include <cpsw.h>
36 #include "board.h"
38 DECLARE_GLOBAL_DATA_PTR;
40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
41 #ifdef CONFIG_SPL_BUILD
42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
43 #endif
45 /* MII mode defines */
46 #define MII_MODE_ENABLE 0x0
47 #define RGMII_MODE_ENABLE 0xA
49 /* GPIO that controls power to DDR on EVM-SK */
50 #define GPIO_DDR_VTT_EN 7
52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
54 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
56 static inline int board_is_bone(void)
57 {
58 return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
59 }
61 static inline int board_is_bone_lt(void)
62 {
63 return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
64 }
66 static inline int board_is_evm_sk(void)
67 {
68 return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
69 }
71 /*
72 * Read header information from EEPROM into global structure.
73 */
74 static int read_eeprom(void)
75 {
76 /* Check if baseboard eeprom is available */
77 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
78 puts("Could not probe the EEPROM; something fundamentally "
79 "wrong on the I2C bus.\n");
80 return -ENODEV;
81 }
83 /* read the eeprom using i2c */
84 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
85 sizeof(header))) {
86 puts("Could not read the EEPROM; something fundamentally"
87 " wrong on the I2C bus.\n");
88 return -EIO;
89 }
91 if (header.magic != 0xEE3355AA) {
92 /*
93 * read the eeprom using i2c again,
94 * but use only a 1 byte address
95 */
96 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
97 (uchar *)&header, sizeof(header))) {
98 puts("Could not read the EEPROM; something "
99 "fundamentally wrong on the I2C bus.\n");
100 return -EIO;
101 }
103 if (header.magic != 0xEE3355AA) {
104 printf("Incorrect magic number (0x%x) in EEPROM\n",
105 header.magic);
106 return -EINVAL;
107 }
108 }
110 return 0;
111 }
113 /* UART Defines */
114 #ifdef CONFIG_SPL_BUILD
115 #define UART_RESET (0x1 << 1)
116 #define UART_CLK_RUNNING_MASK 0x1
117 #define UART_SMART_IDLE_EN (0x1 << 0x3)
119 static void rtc32k_enable(void)
120 {
121 struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
123 /*
124 * Unlock the RTC's registers. For more details please see the
125 * RTC_SS section of the TRM. In order to unlock we need to
126 * write these specific values (keys) in this order.
127 */
128 writel(0x83e70b13, &rtc->kick0r);
129 writel(0x95a4f1e0, &rtc->kick1r);
131 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
132 writel((1 << 3) | (1 << 6), &rtc->osc);
133 }
135 static const struct ddr_data ddr2_data = {
136 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
137 (MT47H128M16RT25E_RD_DQS<<20) |
138 (MT47H128M16RT25E_RD_DQS<<10) |
139 (MT47H128M16RT25E_RD_DQS<<0)),
140 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
141 (MT47H128M16RT25E_WR_DQS<<20) |
142 (MT47H128M16RT25E_WR_DQS<<10) |
143 (MT47H128M16RT25E_WR_DQS<<0)),
144 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
145 (MT47H128M16RT25E_PHY_WRLVL<<20) |
146 (MT47H128M16RT25E_PHY_WRLVL<<10) |
147 (MT47H128M16RT25E_PHY_WRLVL<<0)),
148 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
149 (MT47H128M16RT25E_PHY_GATELVL<<20) |
150 (MT47H128M16RT25E_PHY_GATELVL<<10) |
151 (MT47H128M16RT25E_PHY_GATELVL<<0)),
152 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
153 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
154 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
155 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
156 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
157 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
158 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
159 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
160 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
161 .datadldiff0 = PHY_DLL_LOCK_DIFF,
162 };
164 static const struct cmd_control ddr2_cmd_ctrl_data = {
165 .cmd0csratio = MT47H128M16RT25E_RATIO,
166 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
167 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
169 .cmd1csratio = MT47H128M16RT25E_RATIO,
170 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
171 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
173 .cmd2csratio = MT47H128M16RT25E_RATIO,
174 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
175 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
176 };
178 static const struct emif_regs ddr2_emif_reg_data = {
179 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
180 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
181 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
182 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
183 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
184 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
185 };
187 static const struct ddr_data ddr3_data = {
188 .datardsratio0 = MT41J128MJT125_RD_DQS,
189 .datawdsratio0 = MT41J128MJT125_WR_DQS,
190 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
191 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
192 .datadldiff0 = PHY_DLL_LOCK_DIFF,
193 };
195 static const struct cmd_control ddr3_cmd_ctrl_data = {
196 .cmd0csratio = MT41J128MJT125_RATIO,
197 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
198 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
200 .cmd1csratio = MT41J128MJT125_RATIO,
201 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
202 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
204 .cmd2csratio = MT41J128MJT125_RATIO,
205 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
206 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
207 };
209 static struct emif_regs ddr3_emif_reg_data = {
210 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
211 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
212 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
213 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
214 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
215 .zq_config = MT41J128MJT125_ZQ_CFG,
216 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
217 };
218 #endif
220 /*
221 * early system init of muxing and clocks.
222 */
223 void s_init(void)
224 {
225 /* WDT1 is already running when the bootloader gets control
226 * Disable it to avoid "random" resets
227 */
228 writel(0xAAAA, &wdtimer->wdtwspr);
229 while (readl(&wdtimer->wdtwwps) != 0x0)
230 ;
231 writel(0x5555, &wdtimer->wdtwspr);
232 while (readl(&wdtimer->wdtwwps) != 0x0)
233 ;
235 #ifdef CONFIG_SPL_BUILD
236 /* Setup the PLLs and the clocks for the peripherals */
237 pll_init();
239 /* Enable RTC32K clock */
240 rtc32k_enable();
242 /* UART softreset */
243 u32 regVal;
245 #ifdef CONFIG_SERIAL1
246 enable_uart0_pin_mux();
247 #endif /* CONFIG_SERIAL1 */
248 #ifdef CONFIG_SERIAL2
249 enable_uart1_pin_mux();
250 #endif /* CONFIG_SERIAL2 */
251 #ifdef CONFIG_SERIAL3
252 enable_uart2_pin_mux();
253 #endif /* CONFIG_SERIAL3 */
254 #ifdef CONFIG_SERIAL4
255 enable_uart3_pin_mux();
256 #endif /* CONFIG_SERIAL4 */
257 #ifdef CONFIG_SERIAL5
258 enable_uart4_pin_mux();
259 #endif /* CONFIG_SERIAL5 */
260 #ifdef CONFIG_SERIAL6
261 enable_uart5_pin_mux();
262 #endif /* CONFIG_SERIAL6 */
264 regVal = readl(&uart_base->uartsyscfg);
265 regVal |= UART_RESET;
266 writel(regVal, &uart_base->uartsyscfg);
267 while ((readl(&uart_base->uartsyssts) &
268 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
269 ;
271 /* Disable smart idle */
272 regVal = readl(&uart_base->uartsyscfg);
273 regVal |= UART_SMART_IDLE_EN;
274 writel(regVal, &uart_base->uartsyscfg);
276 gd = &gdata;
278 preloader_console_init();
280 /* Initalize the board header */
281 enable_i2c0_pin_mux();
282 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
283 if (read_eeprom() < 0)
284 puts("Could not get board ID.\n");
286 enable_board_pin_mux(&header);
287 if (board_is_evm_sk()) {
288 /*
289 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
290 * This is safe enough to do on older revs.
291 */
292 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
293 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
294 }
296 if (board_is_evm_sk() || board_is_bone_lt())
297 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
298 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
299 else
300 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
301 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
302 #endif
303 }
305 /*
306 * Basic board specific setup. Pinmux has been handled already.
307 */
308 int board_init(void)
309 {
310 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
311 if (read_eeprom() < 0)
312 puts("Could not get board ID.\n");
314 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
316 return 0;
317 }
319 #ifdef CONFIG_DRIVER_TI_CPSW
320 static void cpsw_control(int enabled)
321 {
322 /* VTP can be added here */
324 return;
325 }
327 static struct cpsw_slave_data cpsw_slaves[] = {
328 {
329 .slave_reg_ofs = 0x208,
330 .sliver_reg_ofs = 0xd80,
331 .phy_id = 0,
332 },
333 {
334 .slave_reg_ofs = 0x308,
335 .sliver_reg_ofs = 0xdc0,
336 .phy_id = 1,
337 },
338 };
340 static struct cpsw_platform_data cpsw_data = {
341 .mdio_base = AM335X_CPSW_MDIO_BASE,
342 .cpsw_base = AM335X_CPSW_BASE,
343 .mdio_div = 0xff,
344 .channels = 8,
345 .cpdma_reg_ofs = 0x800,
346 .slaves = 1,
347 .slave_data = cpsw_slaves,
348 .ale_reg_ofs = 0xd00,
349 .ale_entries = 1024,
350 .host_port_reg_ofs = 0x108,
351 .hw_stats_reg_ofs = 0x900,
352 .mac_control = (1 << 5),
353 .control = cpsw_control,
354 .host_port_num = 0,
355 .version = CPSW_CTRL_VERSION_2,
356 };
358 int board_eth_init(bd_t *bis)
359 {
360 uint8_t mac_addr[6];
361 uint32_t mac_hi, mac_lo;
363 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
364 debug("<ethaddr> not set. Reading from E-fuse\n");
365 /* try reading mac address from efuse */
366 mac_lo = readl(&cdev->macid0l);
367 mac_hi = readl(&cdev->macid0h);
368 mac_addr[0] = mac_hi & 0xFF;
369 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
370 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
371 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
372 mac_addr[4] = mac_lo & 0xFF;
373 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
375 if (is_valid_ether_addr(mac_addr))
376 eth_setenv_enetaddr("ethaddr", mac_addr);
377 else
378 return -1;
379 }
381 if (board_is_bone() || board_is_bone_lt()) {
382 writel(MII_MODE_ENABLE, &cdev->miisel);
383 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
384 PHY_INTERFACE_MODE_MII;
385 } else {
386 writel(RGMII_MODE_ENABLE, &cdev->miisel);
387 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
388 PHY_INTERFACE_MODE_RGMII;
389 }
391 return cpsw_register(&cpsw_data);
392 }
393 #endif