board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29 #include <common.h>
  30 #include <palmas.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/arch/mmc_host_def.h>
  33
  34 #include "mux_data.h"
  35
  36 #ifdef CONFIG_USB_EHCI
  37 #include <usb.h>
  38 #include <asm/arch/ehci.h>
  39 #include <asm/ehci-omap.h>
  40 #endif
  41
  42 #define CTRL_CORE_MPU_IRQ_159_REG                       0x4a002b76
  43 #define CTRL_CORE_MPU_IRQ_155_REG                       0x4a002b6e
  44 #define CTRL_CORE_MPU_IRQ_154_REG                       0x4a002b6c
  45 #define CTRL_CORE_MPU_IRQ_156_REG                       0x4a002b70
  46 #define CTRL_CORE_MPU_IRQ_157_REG                       0x4a002b72
  47 #define CTRL_CORE_MPU_IRQ_136_REG                       0x4a002b48
  48 #define CTRL_CORE_MPU_IRQ_141_REG                       0x4a002b52
  49 #define CTRL_CORE_MPU_IRQ_142_REG                       0x4a002b54
  50 #define CTRL_CORE_MPU_IRQ_143_REG                       0x4a002b56
  51 #define CTRL_CORE_MPU_IRQ_144_REG                       0x4a002b58
  52 #define CTRL_CORE_MPU_IRQ_145_REG                       0x4a002b5a
  53 #define CTRL_CORE_MPU_IRQ_124_REG                       0x4a002b34
  54
  55 #define CTRL_CORE_DMA_SYSTEM_DREQ_79_REG                0x4a002c16
  56 #define CTRL_CORE_DMA_SYSTEM_DREQ_78_REG                0x4a002c14
  57 #define CTRL_CORE_DMA_SYSTEM_DREQ_63_REG                0x4a002bf6
  58 #define CTRL_CORE_DMA_SYSTEM_DREQ_62_REG                0x4a002bf4
  59
  60 DECLARE_GLOBAL_DATA_PTR;
  61
  62 const struct omap_sysinfo sysinfo = {
  63         "Board: DRA7xx\n"
  64 };
  65
  66 /**
  67  * @brief board_init
  68  *
  69  * @return 0
  70  */
  71 int board_init(void)
  72 {
  73         gpmc_init();
  74         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  75
  76         return 0;
  77 }
  78
  79 int board_eth_init(bd_t *bis)
  80 {
  81         return 0;
  82 }
  83
  84 /**
  85  * @brief misc_init_r - Configure EVM board specific configurations
  86  * such as power configurations, ethernet initialization as phase2 of
  87  * boot sequence
  88  *
  89  * @return 0
  90  */
  91 int misc_init_r(void)
  92 {
  93         return 0;
  94 }
  95
  96 static void do_set_mux32(u32 base,
  97                          struct pad_conf_entry const *array, int size)
  98 {
  99         int i;
 100         struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
 101
 102         for (i = 0; i < size; i++, pad++)
 103                 writel(pad->val, base + pad->offset);
 104 }
 105
 106 void set_muxconf_regs_essential(void)
 107 {
 108         do_set_mux32((*ctrl)->control_padconf_core_base,
 109                      core_padconf_array_essential,
 110                      sizeof(core_padconf_array_essential) /
 111                      sizeof(struct pad_conf_entry));
 112 }
 113
 114 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 115 int board_mmc_init(bd_t *bis)
 116 {
 117         omap_mmc_init(0, 0, 0, -1, -1);
 118         omap_mmc_init(1, 0, 0, -1, -1);
 119         return 0;
 120 }
 121 #endif
 122
 123 static void set_crossbar_mpu_irq()
 124 {
 125         /* MPU_IRQ mapping to CROSSBAR_IRQ */
 126         writew(217, CTRL_CORE_MPU_IRQ_159_REG); /* RTC_IRQ */
 127         writew(150, CTRL_CORE_MPU_IRQ_155_REG); /* MCASP3_IRQ_AREVT */
 128         writew(151, CTRL_CORE_MPU_IRQ_154_REG); /* MCASP3_IRQ_AXEVT */
 129         writew(156, CTRL_CORE_MPU_IRQ_156_REG); /* MCASP6_IRQ_AREVT */
 130         writew(157, CTRL_CORE_MPU_IRQ_157_REG); /* MCASP6_IRQ_AXEVT */
 131         writew(251, CTRL_CORE_MPU_IRQ_136_REG); /* MAILBOX5 */
 132         writew(255, CTRL_CORE_MPU_IRQ_141_REG); /* MAILBOX6 */
 133         writew(396, CTRL_CORE_MPU_IRQ_142_REG); /* IPU2 MMU */
 134         writew(145, CTRL_CORE_MPU_IRQ_143_REG); /* DSP1 MMU1 */
 135         writew(146, CTRL_CORE_MPU_IRQ_144_REG); /* DSP2 MMU0 */
 136         writew(147, CTRL_CORE_MPU_IRQ_145_REG); /* DSP2 MMU1 */
 137         writew(343, CTRL_CORE_MPU_IRQ_124_REG); /* QSPI */
 138 }
 139
 140 static void set_crossbar_sdma_dreq()
 141 {
 142         /* SDMA_DREQ mapping to CROSSBAR_IRQ */
 143         writew(132, CTRL_CORE_DMA_SYSTEM_DREQ_79_REG);  /* MCASP3_DREQ_RX */
 144         writew(133, CTRL_CORE_DMA_SYSTEM_DREQ_78_REG);  /* MCASP3_DREQ_TX */
 145         writew(138, CTRL_CORE_DMA_SYSTEM_DREQ_63_REG);  /* MCASP6_DREQ_RX */
 146         writew(139, CTRL_CORE_DMA_SYSTEM_DREQ_62_REG);  /* MCASP6_DREQ_TX */
 147 }
 148
 149 void set_crossbar_regs(void)
 150 {
 151         set_crossbar_mpu_irq();
 152         set_crossbar_sdma_dreq();
 153 }