bbd71d47fa508ec981ba896c695320de0671823b
[glsdk/glsdk-u-boot.git] / board / ti / dra7xx / evm.c
1 /*
2  * (C) Copyright 2013
3  * Texas Instruments Incorporated, <www.ti.com>
4  *
5  * Lokesh Vutla <lokeshvutla@ti.com>
6  *
7  * Based on previous work by:
8  * Aneesh V       <aneesh@ti.com>
9  * Steve Sakoman  <steve@sakoman.com>
10  *
11  * See file CREDITS for list of people who contributed to this
12  * project.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27  * MA 02111-1307 USA
28  */
29 #include <common.h>
30 #include <palmas.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/mmc_host_def.h>
34 #include "mux_data.h"
36 #ifdef CONFIG_USB_EHCI
37 #include <usb.h>
38 #include <asm/arch/ehci.h>
39 #include <asm/ehci-omap.h>
40 #endif
42 #ifdef CONFIG_DRIVER_TI_CPSW
43 #include <cpsw.h>
44 #endif
46 #define CTRL_CORE_MPU_IRQ_159_REG                       0x4a002b76
47 #define CTRL_CORE_MPU_IRQ_155_REG                       0x4a002b6e
48 #define CTRL_CORE_MPU_IRQ_154_REG                       0x4a002b6c
49 #define CTRL_CORE_MPU_IRQ_156_REG                       0x4a002b70
50 #define CTRL_CORE_MPU_IRQ_157_REG                       0x4a002b72
51 #define CTRL_CORE_MPU_IRQ_136_REG                       0x4a002b48
52 #define CTRL_CORE_MPU_IRQ_141_REG                       0x4a002b52
53 #define CTRL_CORE_MPU_IRQ_142_REG                       0x4a002b54
54 #define CTRL_CORE_MPU_IRQ_143_REG                       0x4a002b56
55 #define CTRL_CORE_MPU_IRQ_144_REG                       0x4a002b58
56 #define CTRL_CORE_MPU_IRQ_145_REG                       0x4a002b5a
57 #define CTRL_CORE_MPU_IRQ_124_REG                       0x4a002b34
58 #define CTRL_CORE_MPU_IRQ_50_REG                        0x4a002aa0
59 #define CTRL_CORE_MPU_IRQ_51_REG                        0x4a002aa2
60 #define CTRL_CORE_MPU_IRQ_52_REG                        0x4a002aa4
61 #define CTRL_CORE_MPU_IRQ_53_REG                        0x4a002aa6
63 #define CTRL_CORE_DMA_SYSTEM_DREQ_79_REG                0x4a002c16
64 #define CTRL_CORE_DMA_SYSTEM_DREQ_78_REG                0x4a002c14
65 #define CTRL_CORE_DMA_SYSTEM_DREQ_63_REG                0x4a002bf6
66 #define CTRL_CORE_DMA_SYSTEM_DREQ_62_REG                0x4a002bf4
68 DECLARE_GLOBAL_DATA_PTR;
70 const struct omap_sysinfo sysinfo = {
71         "Board: DRA7xx\n"
72 };
74 /*
75  * Adjust I/O delays on the Tx control and data lines of each MAC port. This
76  * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
77  * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
78  * essentially need to counteract the DRA7xx internal delay, and we do this
79  * by delaying the control and data lines. If not using this PHY, you probably
80  * don't need to do this stuff!
81  */
82 static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
83 {
84         int i = 0;
85         u32 reg_val;
86         u32 delta;
87         u32 coarse;
88         u32 fine;
90         writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
92         while(io_dly[i].addr) {
93                 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
94                        io_dly[i].addr);
95                 delta = io_dly[i].dly;
96                 reg_val = readl(io_dly[i].addr) & 0x3ff;
97                 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
98                 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
99                 fine = (reg_val & 0x1F) + (delta & 0x1F);
100                 fine = (fine > 0x1F) ? (0x1F) : (fine);
101                 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
102                                 CFG_IO_DELAY_LOCK_MASK |
103                                 ((coarse << 5) | (fine));
104                 writel(reg_val, io_dly[i].addr);
105                 i++;
106         }
108         writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
111 /**
112  * @brief board_init
113  *
114  * @return 0
115  */
116 int board_init(void)
118         gpmc_init();
119         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
121         return 0;
124 /**
125  * @brief misc_init_r - Configure EVM board specific configurations
126  * such as power configurations, ethernet initialization as phase2 of
127  * boot sequence
128  *
129  * @return 0
130  */
131 int misc_init_r(void)
133         return 0;
136 static void do_set_mux32(u32 base,
137                          struct pad_conf_entry const *array, int size)
139         int i;
140         struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
142         for (i = 0; i < size; i++, pad++)
143                 writel(pad->val, base + pad->offset);
146 void set_muxconf_regs_essential(void)
148         do_set_mux32((*ctrl)->control_padconf_core_base,
149                      core_padconf_array_essential,
150                      sizeof(core_padconf_array_essential) /
151                      sizeof(struct pad_conf_entry));
154 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
155 int board_mmc_init(bd_t *bis)
157         omap_mmc_init(0, 0, 0, -1, -1);
158         omap_mmc_init(1, 0, 0, -1, -1);
159         return 0;
161 #endif
163 static void set_crossbar_mpu_irq()
165         /* MPU_IRQ mapping to CROSSBAR_IRQ */
166         writew(217, CTRL_CORE_MPU_IRQ_159_REG); /* RTC_IRQ */
167         writew(150, CTRL_CORE_MPU_IRQ_155_REG); /* MCASP3_IRQ_AREVT */
168         writew(151, CTRL_CORE_MPU_IRQ_154_REG); /* MCASP3_IRQ_AXEVT */
169         writew(156, CTRL_CORE_MPU_IRQ_156_REG); /* MCASP6_IRQ_AREVT */
170         writew(157, CTRL_CORE_MPU_IRQ_157_REG); /* MCASP6_IRQ_AXEVT */
171         writew(251, CTRL_CORE_MPU_IRQ_136_REG); /* MAILBOX5 */
172         writew(255, CTRL_CORE_MPU_IRQ_141_REG); /* MAILBOX6 */
173         writew(396, CTRL_CORE_MPU_IRQ_142_REG); /* IPU2 MMU */
174         writew(145, CTRL_CORE_MPU_IRQ_143_REG); /* DSP1 MMU1 */
175         writew(146, CTRL_CORE_MPU_IRQ_144_REG); /* DSP2 MMU0 */
176         writew(147, CTRL_CORE_MPU_IRQ_145_REG); /* DSP2 MMU1 */
177         writew(343, CTRL_CORE_MPU_IRQ_124_REG); /* QSPI */
178         writew(334, CTRL_CORE_MPU_IRQ_50_REG);  /* CPSW_RX_THRESH */
179         writew(335, CTRL_CORE_MPU_IRQ_51_REG);  /* CPSW_RX */
180         writew(336, CTRL_CORE_MPU_IRQ_52_REG);  /* CPSW_TX */
181         writew(337, CTRL_CORE_MPU_IRQ_53_REG);  /* CPSW_MISC */
184 static void set_crossbar_sdma_dreq()
186         /* SDMA_DREQ mapping to CROSSBAR_IRQ */
187         writew(132, CTRL_CORE_DMA_SYSTEM_DREQ_79_REG);  /* MCASP3_DREQ_RX */
188         writew(133, CTRL_CORE_DMA_SYSTEM_DREQ_78_REG);  /* MCASP3_DREQ_TX */
189         writew(138, CTRL_CORE_DMA_SYSTEM_DREQ_63_REG);  /* MCASP6_DREQ_RX */
190         writew(139, CTRL_CORE_DMA_SYSTEM_DREQ_62_REG);  /* MCASP6_DREQ_TX */
193 void set_crossbar_regs(void)
195         set_crossbar_mpu_irq();
196         set_crossbar_sdma_dreq();
199 #ifdef CONFIG_DRIVER_TI_CPSW
201 /* Delay value to add to calibrated value */
202 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
203 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
204 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
205 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
206 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
207 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
208 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
209 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
210 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
211 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
213 static void cpsw_control(int enabled)
215         /* VTP can be added here */
217         return;
220 static struct cpsw_slave_data cpsw_slaves[] = {
221         {
222                 .slave_reg_ofs  = 0x208,
223                 .sliver_reg_ofs = 0xd80,
224                 .phy_id         = 0,
225         },
226         {
227                 .slave_reg_ofs  = 0x308,
228                 .sliver_reg_ofs = 0xdc0,
229                 .phy_id         = 1,
230         },
231 };
233 static struct cpsw_platform_data cpsw_data = {
234         .mdio_base              = CPSW_MDIO_BASE,
235         .cpsw_base              = CPSW_BASE,
236         .mdio_div               = 0xff,
237         .channels               = 8,
238         .cpdma_reg_ofs          = 0x800,
239         .slaves                 = 1,
240         .slave_data             = cpsw_slaves,
241         .ale_reg_ofs            = 0xd00,
242         .ale_entries            = 1024,
243         .host_port_reg_ofs      = 0x108,
244         .hw_stats_reg_ofs       = 0x900,
245         .bd_ram_ofs             = 0x2000,
246         .mac_control            = (1 << 5),
247         .control                = cpsw_control,
248         .host_port_num          = 0,
249         .version                = CPSW_CTRL_VERSION_2,
250 };
252 int board_eth_init(bd_t *bis)
254         int ret;
255         uint8_t mac_addr[6];
256         uint32_t mac_hi, mac_lo;
257         uint32_t ctrl_val;
258         const struct io_delay io_dly[] = {
259                 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
260                 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
261                 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
262                 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
263                 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
264                 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
265                 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
266                 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
267                 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
268                 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
269                 {0}
270         };
272         /* Adjust IO delay for RGMII tx path */
273         dra7xx_adj_io_delay(io_dly);
275         /* try reading mac address from efuse */
276         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
277         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
278         mac_addr[0] = mac_hi & 0xFF;
279         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
280         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
281         mac_addr[3] = mac_lo & 0xFF;
282         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
283         mac_addr[5] = (mac_lo & 0xFF0000) >> 16;
285         if (!getenv("ethaddr")) {
286                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
288                 if (is_valid_ether_addr(mac_addr))
289                         eth_setenv_enetaddr("ethaddr", mac_addr);
290         }
291         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
292         ctrl_val |= 0x22;
293         writel(ctrl_val, (*ctrl)->control_core_control_io1);
295         ret = cpsw_register(&cpsw_data);
296         if (ret < 0)
297                 printf("Error %d registering CPSW switch\n", ret);
299         return ret;
301 #endif