HACK: ARM: DRA7xx: Add Ethernet crossbar setting
[glsdk/glsdk-u-boot.git] / board / ti / dra7xx / evm.c
1 /*
2  * (C) Copyright 2013
3  * Texas Instruments Incorporated, <www.ti.com>
4  *
5  * Lokesh Vutla <lokeshvutla@ti.com>
6  *
7  * Based on previous work by:
8  * Aneesh V       <aneesh@ti.com>
9  * Steve Sakoman  <steve@sakoman.com>
10  *
11  * See file CREDITS for list of people who contributed to this
12  * project.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27  * MA 02111-1307 USA
28  */
29 #include <common.h>
30 #include <palmas.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/mmc_host_def.h>
34 #include "mux_data.h"
36 #ifdef CONFIG_USB_EHCI
37 #include <usb.h>
38 #include <asm/arch/ehci.h>
39 #include <asm/ehci-omap.h>
40 #endif
42 #define CTRL_CORE_MPU_IRQ_159_REG                       0x4a002b76
43 #define CTRL_CORE_MPU_IRQ_155_REG                       0x4a002b6e
44 #define CTRL_CORE_MPU_IRQ_154_REG                       0x4a002b6c
45 #define CTRL_CORE_MPU_IRQ_156_REG                       0x4a002b70
46 #define CTRL_CORE_MPU_IRQ_157_REG                       0x4a002b72
47 #define CTRL_CORE_MPU_IRQ_136_REG                       0x4a002b48
48 #define CTRL_CORE_MPU_IRQ_141_REG                       0x4a002b52
49 #define CTRL_CORE_MPU_IRQ_142_REG                       0x4a002b54
50 #define CTRL_CORE_MPU_IRQ_143_REG                       0x4a002b56
51 #define CTRL_CORE_MPU_IRQ_144_REG                       0x4a002b58
52 #define CTRL_CORE_MPU_IRQ_145_REG                       0x4a002b5a
53 #define CTRL_CORE_MPU_IRQ_124_REG                       0x4a002b34
54 #define CTRL_CORE_MPU_IRQ_50_REG                        0x4a002aa0
55 #define CTRL_CORE_MPU_IRQ_51_REG                        0x4a002aa2
56 #define CTRL_CORE_MPU_IRQ_52_REG                        0x4a002aa4
57 #define CTRL_CORE_MPU_IRQ_53_REG                        0x4a002aa6
59 #define CTRL_CORE_DMA_SYSTEM_DREQ_79_REG                0x4a002c16
60 #define CTRL_CORE_DMA_SYSTEM_DREQ_78_REG                0x4a002c14
61 #define CTRL_CORE_DMA_SYSTEM_DREQ_63_REG                0x4a002bf6
62 #define CTRL_CORE_DMA_SYSTEM_DREQ_62_REG                0x4a002bf4
64 DECLARE_GLOBAL_DATA_PTR;
66 const struct omap_sysinfo sysinfo = {
67         "Board: DRA7xx\n"
68 };
70 /**
71  * @brief board_init
72  *
73  * @return 0
74  */
75 int board_init(void)
76 {
77         gpmc_init();
78         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
80         return 0;
81 }
83 int board_eth_init(bd_t *bis)
84 {
85         return 0;
86 }
88 /**
89  * @brief misc_init_r - Configure EVM board specific configurations
90  * such as power configurations, ethernet initialization as phase2 of
91  * boot sequence
92  *
93  * @return 0
94  */
95 int misc_init_r(void)
96 {
97         return 0;
98 }
100 static void do_set_mux32(u32 base,
101                          struct pad_conf_entry const *array, int size)
103         int i;
104         struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
106         for (i = 0; i < size; i++, pad++)
107                 writel(pad->val, base + pad->offset);
110 void set_muxconf_regs_essential(void)
112         do_set_mux32((*ctrl)->control_padconf_core_base,
113                      core_padconf_array_essential,
114                      sizeof(core_padconf_array_essential) /
115                      sizeof(struct pad_conf_entry));
118 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
119 int board_mmc_init(bd_t *bis)
121         omap_mmc_init(0, 0, 0, -1, -1);
122         omap_mmc_init(1, 0, 0, -1, -1);
123         return 0;
125 #endif
127 static void set_crossbar_mpu_irq()
129         /* MPU_IRQ mapping to CROSSBAR_IRQ */
130         writew(217, CTRL_CORE_MPU_IRQ_159_REG); /* RTC_IRQ */
131         writew(150, CTRL_CORE_MPU_IRQ_155_REG); /* MCASP3_IRQ_AREVT */
132         writew(151, CTRL_CORE_MPU_IRQ_154_REG); /* MCASP3_IRQ_AXEVT */
133         writew(156, CTRL_CORE_MPU_IRQ_156_REG); /* MCASP6_IRQ_AREVT */
134         writew(157, CTRL_CORE_MPU_IRQ_157_REG); /* MCASP6_IRQ_AXEVT */
135         writew(251, CTRL_CORE_MPU_IRQ_136_REG); /* MAILBOX5 */
136         writew(255, CTRL_CORE_MPU_IRQ_141_REG); /* MAILBOX6 */
137         writew(396, CTRL_CORE_MPU_IRQ_142_REG); /* IPU2 MMU */
138         writew(145, CTRL_CORE_MPU_IRQ_143_REG); /* DSP1 MMU1 */
139         writew(146, CTRL_CORE_MPU_IRQ_144_REG); /* DSP2 MMU0 */
140         writew(147, CTRL_CORE_MPU_IRQ_145_REG); /* DSP2 MMU1 */
141         writew(343, CTRL_CORE_MPU_IRQ_124_REG); /* QSPI */
142         writew(334, CTRL_CORE_MPU_IRQ_50_REG);  /* CPSW_RX_THRESH */
143         writew(335, CTRL_CORE_MPU_IRQ_51_REG);  /* CPSW_RX */
144         writew(336, CTRL_CORE_MPU_IRQ_52_REG);  /* CPSW_TX */
145         writew(337, CTRL_CORE_MPU_IRQ_53_REG);  /* CPSW_MISC */
148 static void set_crossbar_sdma_dreq()
150         /* SDMA_DREQ mapping to CROSSBAR_IRQ */
151         writew(132, CTRL_CORE_DMA_SYSTEM_DREQ_79_REG);  /* MCASP3_DREQ_RX */
152         writew(133, CTRL_CORE_DMA_SYSTEM_DREQ_78_REG);  /* MCASP3_DREQ_TX */
153         writew(138, CTRL_CORE_DMA_SYSTEM_DREQ_63_REG);  /* MCASP6_DREQ_RX */
154         writew(139, CTRL_CORE_DMA_SYSTEM_DREQ_62_REG);  /* MCASP6_DREQ_TX */
157 void set_crossbar_regs(void)
159         set_crossbar_mpu_irq();
160         set_crossbar_sdma_dreq();