1 /*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 /*
25 * I2C Functions similar to the standard memory functions.
26 *
27 * There are several parameters in many of the commands that bear further
28 * explanations:
29 *
30 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
31 * Each I2C chip on the bus has a unique address. On the I2C data bus,
32 * the address is the upper seven bits and the LSB is the "read/write"
33 * bit. Note that the {i2c_chip} address specified on the command
34 * line is not shifted up: e.g. a typical EEPROM memory chip may have
35 * an I2C address of 0x50, but the data put on the bus will be 0xA0
36 * for write and 0xA1 for read. This "non shifted" address notation
37 * matches at least half of the data sheets :-/.
38 *
39 * {addr} is the address (or offset) within the chip. Small memory
40 * chips have 8 bit addresses. Large memory chips have 16 bit
41 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
42 * Many non-memory chips have multiple registers and {addr} is used
43 * as the register index. Some non-memory chips have only one register
44 * and therefore don't need any {addr} parameter.
45 *
46 * The default {addr} parameter is one byte (.1) which works well for
47 * memories and registers with 8 bits of address space.
48 *
49 * You can specify the length of the {addr} field with the optional .0,
50 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
51 * manipulating a single register device which doesn't use an address
52 * field, use "0.0" for the address and the ".0" length field will
53 * suppress the address in the I2C data stream. This also works for
54 * successive reads using the I2C auto-incrementing memory pointer.
55 *
56 * If you are manipulating a large memory with 2-byte addresses, use
57 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
58 *
59 * Then there are the unfortunate memory chips that spill the most
60 * significant 1, 2, or 3 bits of address into the chip address byte.
61 * This effectively makes one chip (logically) look like 2, 4, or
62 * 8 chips. This is handled (awkwardly) by #defining
63 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
64 * {addr} field (since .1 is the default, it doesn't actually have to
65 * be specified). Examples: given a memory chip at I2C chip address
66 * 0x50, the following would happen...
67 * i2c md 50 0 10 display 16 bytes starting at 0x000
68 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
69 * i2c md 50 100 10 display 16 bytes starting at 0x100
70 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
71 * i2c md 50 210 10 display 16 bytes starting at 0x210
72 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
73 * This is awfully ugly. It would be nice if someone would think up
74 * a better way of handling this.
75 *
76 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
77 */
79 #include <common.h>
80 #include <command.h>
81 #include <environment.h>
82 #include <i2c.h>
83 #include <malloc.h>
84 #include <asm/byteorder.h>
86 /* Display values from last command.
87 * Memory modify remembered values are different from display memory.
88 */
89 static uchar i2c_dp_last_chip;
90 static uint i2c_dp_last_addr;
91 static uint i2c_dp_last_alen;
92 static uint i2c_dp_last_length = 0x10;
94 static uchar i2c_mm_last_chip;
95 static uint i2c_mm_last_addr;
96 static uint i2c_mm_last_alen;
98 /* If only one I2C bus is present, the list of devices to ignore when
99 * the probe command is issued is represented by a 1D array of addresses.
100 * When multiple buses are present, the list is an array of bus-address
101 * pairs. The following macros take care of this */
103 #if defined(CONFIG_SYS_I2C_NOPROBES)
104 #if defined(CONFIG_I2C_MULTI_BUS)
105 static struct
106 {
107 uchar bus;
108 uchar addr;
109 } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
110 #define GET_BUS_NUM i2c_get_bus_num()
111 #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
112 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
113 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
114 #else /* single bus */
115 static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
116 #define GET_BUS_NUM 0
117 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
118 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
119 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
120 #endif /* CONFIG_MULTI_BUS */
122 #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
123 #endif
125 #if defined(CONFIG_I2C_MUX)
126 static I2C_MUX_DEVICE *i2c_mux_devices = NULL;
127 static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
129 DECLARE_GLOBAL_DATA_PTR;
131 #endif
133 #define DISP_LINE_LEN 16
135 /* implement possible board specific board init */
136 void __def_i2c_init_board(void)
137 {
138 return;
139 }
140 void i2c_init_board(void)
141 __attribute__((weak, alias("__def_i2c_init_board")));
143 /* TODO: Implement architecture-specific get/set functions */
144 unsigned int __def_i2c_get_bus_speed(void)
145 {
146 return CONFIG_SYS_I2C_SPEED;
147 }
148 unsigned int i2c_get_bus_speed(void)
149 __attribute__((weak, alias("__def_i2c_get_bus_speed")));
151 int __def_i2c_set_bus_speed(unsigned int speed)
152 {
153 if (speed != CONFIG_SYS_I2C_SPEED)
154 return -1;
156 return 0;
157 }
158 int i2c_set_bus_speed(unsigned int)
159 __attribute__((weak, alias("__def_i2c_set_bus_speed")));
161 /*
162 * get_alen: small parser helper function to get address length
163 * returns the address length
164 */
165 static uint get_alen(char *arg)
166 {
167 int j;
168 int alen;
170 alen = 1;
171 for (j = 0; j < 8; j++) {
172 if (arg[j] == '.') {
173 alen = arg[j+1] - '0';
174 break;
175 } else if (arg[j] == '\0')
176 break;
177 }
178 return alen;
179 }
181 /*
182 * Syntax:
183 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
184 */
186 static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
187 {
188 u_char chip;
189 uint devaddr, alen, length;
190 u_char *memaddr;
192 if (argc != 5)
193 return CMD_RET_USAGE;
195 /*
196 * I2C chip address
197 */
198 chip = simple_strtoul(argv[1], NULL, 16);
200 /*
201 * I2C data address within the chip. This can be 1 or
202 * 2 bytes long. Some day it might be 3 bytes long :-).
203 */
204 devaddr = simple_strtoul(argv[2], NULL, 16);
205 alen = get_alen(argv[2]);
206 if (alen > 3)
207 return CMD_RET_USAGE;
209 /*
210 * Length is the number of objects, not number of bytes.
211 */
212 length = simple_strtoul(argv[3], NULL, 16);
214 /*
215 * memaddr is the address where to store things in memory
216 */
217 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
219 if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
220 puts ("Error reading the chip.\n");
221 return 1;
222 }
223 return 0;
224 }
226 static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
227 {
228 u_char chip;
229 uint devaddr, alen, length;
230 u_char *memaddr;
232 if (argc != 5)
233 return cmd_usage(cmdtp);
235 /*
236 * memaddr is the address where to store things in memory
237 */
238 memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
240 /*
241 * I2C chip address
242 */
243 chip = simple_strtoul(argv[2], NULL, 16);
245 /*
246 * I2C data address within the chip. This can be 1 or
247 * 2 bytes long. Some day it might be 3 bytes long :-).
248 */
249 devaddr = simple_strtoul(argv[3], NULL, 16);
250 alen = get_alen(argv[3]);
251 if (alen > 3)
252 return cmd_usage(cmdtp);
254 /*
255 * Length is the number of objects, not number of bytes.
256 */
257 length = simple_strtoul(argv[4], NULL, 16);
259 while (length-- > 0) {
260 if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
261 puts("Error writing to the chip.\n");
262 return 1;
263 }
264 /*
265 * No write delay with FRAM devices.
266 */
267 #if !defined(CONFIG_SYS_I2C_FRAM)
268 udelay(11000);
269 #endif
270 }
271 return 0;
272 }
274 /*
275 * Syntax:
276 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
277 */
278 static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
279 {
280 u_char chip;
281 uint addr, alen, length;
282 int j, nbytes, linebytes;
284 /* We use the last specified parameters, unless new ones are
285 * entered.
286 */
287 chip = i2c_dp_last_chip;
288 addr = i2c_dp_last_addr;
289 alen = i2c_dp_last_alen;
290 length = i2c_dp_last_length;
292 if (argc < 3)
293 return CMD_RET_USAGE;
295 if ((flag & CMD_FLAG_REPEAT) == 0) {
296 /*
297 * New command specified.
298 */
300 /*
301 * I2C chip address
302 */
303 chip = simple_strtoul(argv[1], NULL, 16);
305 /*
306 * I2C data address within the chip. This can be 1 or
307 * 2 bytes long. Some day it might be 3 bytes long :-).
308 */
309 addr = simple_strtoul(argv[2], NULL, 16);
310 alen = get_alen(argv[2]);
311 if (alen > 3)
312 return CMD_RET_USAGE;
314 /*
315 * If another parameter, it is the length to display.
316 * Length is the number of objects, not number of bytes.
317 */
318 if (argc > 3)
319 length = simple_strtoul(argv[3], NULL, 16);
320 }
322 /*
323 * Print the lines.
324 *
325 * We buffer all read data, so we can make sure data is read only
326 * once.
327 */
328 nbytes = length;
329 do {
330 unsigned char linebuf[DISP_LINE_LEN];
331 unsigned char *cp;
333 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
335 if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
336 puts ("Error reading the chip.\n");
337 else {
338 printf("%04x:", addr);
339 cp = linebuf;
340 for (j=0; j<linebytes; j++) {
341 printf(" %02x", *cp++);
342 addr++;
343 }
344 puts (" ");
345 cp = linebuf;
346 for (j=0; j<linebytes; j++) {
347 if ((*cp < 0x20) || (*cp > 0x7e))
348 puts (".");
349 else
350 printf("%c", *cp);
351 cp++;
352 }
353 putc ('\n');
354 }
355 nbytes -= linebytes;
356 } while (nbytes > 0);
358 i2c_dp_last_chip = chip;
359 i2c_dp_last_addr = addr;
360 i2c_dp_last_alen = alen;
361 i2c_dp_last_length = length;
363 return 0;
364 }
367 /* Write (fill) memory
368 *
369 * Syntax:
370 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
371 */
372 static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
373 {
374 uchar chip;
375 ulong addr;
376 uint alen;
377 uchar byte;
378 int count;
380 if ((argc < 4) || (argc > 5))
381 return CMD_RET_USAGE;
383 /*
384 * Chip is always specified.
385 */
386 chip = simple_strtoul(argv[1], NULL, 16);
388 /*
389 * Address is always specified.
390 */
391 addr = simple_strtoul(argv[2], NULL, 16);
392 alen = get_alen(argv[2]);
393 if (alen > 3)
394 return CMD_RET_USAGE;
396 /*
397 * Value to write is always specified.
398 */
399 byte = simple_strtoul(argv[3], NULL, 16);
401 /*
402 * Optional count
403 */
404 if (argc == 5)
405 count = simple_strtoul(argv[4], NULL, 16);
406 else
407 count = 1;
409 while (count-- > 0) {
410 if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
411 puts ("Error writing the chip.\n");
412 /*
413 * Wait for the write to complete. The write can take
414 * up to 10mSec (we allow a little more time).
415 */
416 /*
417 * No write delay with FRAM devices.
418 */
419 #if !defined(CONFIG_SYS_I2C_FRAM)
420 udelay(11000);
421 #endif
422 }
424 return (0);
425 }
427 /* Calculate a CRC on memory
428 *
429 * Syntax:
430 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
431 */
432 static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
433 {
434 uchar chip;
435 ulong addr;
436 uint alen;
437 int count;
438 uchar byte;
439 ulong crc;
440 ulong err;
442 if (argc < 4)
443 return CMD_RET_USAGE;
445 /*
446 * Chip is always specified.
447 */
448 chip = simple_strtoul(argv[1], NULL, 16);
450 /*
451 * Address is always specified.
452 */
453 addr = simple_strtoul(argv[2], NULL, 16);
454 alen = get_alen(argv[2]);
455 if (alen > 3)
456 return CMD_RET_USAGE;
458 /*
459 * Count is always specified
460 */
461 count = simple_strtoul(argv[3], NULL, 16);
463 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
464 /*
465 * CRC a byte at a time. This is going to be slooow, but hey, the
466 * memories are small and slow too so hopefully nobody notices.
467 */
468 crc = 0;
469 err = 0;
470 while (count-- > 0) {
471 if (i2c_read(chip, addr, alen, &byte, 1) != 0)
472 err++;
473 crc = crc32 (crc, &byte, 1);
474 addr++;
475 }
476 if (err > 0)
477 puts ("Error reading the chip,\n");
478 else
479 printf ("%08lx\n", crc);
481 return 0;
482 }
484 /* Modify memory.
485 *
486 * Syntax:
487 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
488 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
489 */
491 static int
492 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
493 {
494 uchar chip;
495 ulong addr;
496 uint alen;
497 ulong data;
498 int size = 1;
499 int nbytes;
501 if (argc != 3)
502 return CMD_RET_USAGE;
504 #ifdef CONFIG_BOOT_RETRY_TIME
505 reset_cmd_timeout(); /* got a good command to get here */
506 #endif
507 /*
508 * We use the last specified parameters, unless new ones are
509 * entered.
510 */
511 chip = i2c_mm_last_chip;
512 addr = i2c_mm_last_addr;
513 alen = i2c_mm_last_alen;
515 if ((flag & CMD_FLAG_REPEAT) == 0) {
516 /*
517 * New command specified. Check for a size specification.
518 * Defaults to byte if no or incorrect specification.
519 */
520 size = cmd_get_data_size(argv[0], 1);
522 /*
523 * Chip is always specified.
524 */
525 chip = simple_strtoul(argv[1], NULL, 16);
527 /*
528 * Address is always specified.
529 */
530 addr = simple_strtoul(argv[2], NULL, 16);
531 alen = get_alen(argv[2]);
532 if (alen > 3)
533 return CMD_RET_USAGE;
534 }
536 /*
537 * Print the address, followed by value. Then accept input for
538 * the next value. A non-converted value exits.
539 */
540 do {
541 printf("%08lx:", addr);
542 if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
543 puts ("\nError reading the chip,\n");
544 else {
545 data = cpu_to_be32(data);
546 if (size == 1)
547 printf(" %02lx", (data >> 24) & 0x000000FF);
548 else if (size == 2)
549 printf(" %04lx", (data >> 16) & 0x0000FFFF);
550 else
551 printf(" %08lx", data);
552 }
554 nbytes = readline (" ? ");
555 if (nbytes == 0) {
556 /*
557 * <CR> pressed as only input, don't modify current
558 * location and move to next.
559 */
560 if (incrflag)
561 addr += size;
562 nbytes = size;
563 #ifdef CONFIG_BOOT_RETRY_TIME
564 reset_cmd_timeout(); /* good enough to not time out */
565 #endif
566 }
567 #ifdef CONFIG_BOOT_RETRY_TIME
568 else if (nbytes == -2)
569 break; /* timed out, exit the command */
570 #endif
571 else {
572 char *endp;
574 data = simple_strtoul(console_buffer, &endp, 16);
575 if (size == 1)
576 data = data << 24;
577 else if (size == 2)
578 data = data << 16;
579 data = be32_to_cpu(data);
580 nbytes = endp - console_buffer;
581 if (nbytes) {
582 #ifdef CONFIG_BOOT_RETRY_TIME
583 /*
584 * good enough to not time out
585 */
586 reset_cmd_timeout();
587 #endif
588 if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
589 puts ("Error writing the chip.\n");
590 #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
591 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
592 #endif
593 if (incrflag)
594 addr += size;
595 }
596 }
597 } while (nbytes);
599 i2c_mm_last_chip = chip;
600 i2c_mm_last_addr = addr;
601 i2c_mm_last_alen = alen;
603 return 0;
604 }
606 /*
607 * Syntax:
608 * i2c probe {addr}
609 *
610 * Returns zero (success) if one or more I2C devices was found
611 */
612 static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
613 {
614 int j;
615 int addr = -1;
616 int found = 0;
617 #if defined(CONFIG_SYS_I2C_NOPROBES)
618 int k, skip;
619 uchar bus = GET_BUS_NUM;
620 #endif /* NOPROBES */
622 if (argc == 2)
623 addr = simple_strtol(argv[1], 0, 16);
625 puts ("Valid chip addresses:");
626 for (j = 0; j < 128; j++) {
627 if ((0 <= addr) && (j != addr))
628 continue;
630 #if defined(CONFIG_SYS_I2C_NOPROBES)
631 skip = 0;
632 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
633 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
634 skip = 1;
635 break;
636 }
637 }
638 if (skip)
639 continue;
640 #endif
641 if (i2c_probe(j) == 0) {
642 printf(" %02X", j);
643 found++;
644 }
645 }
646 putc ('\n');
648 #if defined(CONFIG_SYS_I2C_NOPROBES)
649 puts ("Excluded chip addresses:");
650 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
651 if (COMPARE_BUS(bus,k))
652 printf(" %02X", NO_PROBE_ADDR(k));
653 }
654 putc ('\n');
655 #endif
657 return (0 == found);
658 }
660 /*
661 * Syntax:
662 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
663 * {length} - Number of bytes to read
664 * {delay} - A DECIMAL number and defaults to 1000 uSec
665 */
666 static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
667 {
668 u_char chip;
669 ulong alen;
670 uint addr;
671 uint length;
672 u_char bytes[16];
673 int delay;
675 if (argc < 3)
676 return CMD_RET_USAGE;
678 /*
679 * Chip is always specified.
680 */
681 chip = simple_strtoul(argv[1], NULL, 16);
683 /*
684 * Address is always specified.
685 */
686 addr = simple_strtoul(argv[2], NULL, 16);
687 alen = get_alen(argv[2]);
688 if (alen > 3)
689 return CMD_RET_USAGE;
691 /*
692 * Length is the number of objects, not number of bytes.
693 */
694 length = 1;
695 length = simple_strtoul(argv[3], NULL, 16);
696 if (length > sizeof(bytes))
697 length = sizeof(bytes);
699 /*
700 * The delay time (uSec) is optional.
701 */
702 delay = 1000;
703 if (argc > 3)
704 delay = simple_strtoul(argv[4], NULL, 10);
705 /*
706 * Run the loop...
707 */
708 while (1) {
709 if (i2c_read(chip, addr, alen, bytes, length) != 0)
710 puts ("Error reading the chip.\n");
711 udelay(delay);
712 }
714 /* NOTREACHED */
715 return 0;
716 }
718 /*
719 * The SDRAM command is separately configured because many
720 * (most?) embedded boards don't use SDRAM DIMMs.
721 */
722 #if defined(CONFIG_CMD_SDRAM)
723 static void print_ddr2_tcyc (u_char const b)
724 {
725 printf ("%d.", (b >> 4) & 0x0F);
726 switch (b & 0x0F) {
727 case 0x0:
728 case 0x1:
729 case 0x2:
730 case 0x3:
731 case 0x4:
732 case 0x5:
733 case 0x6:
734 case 0x7:
735 case 0x8:
736 case 0x9:
737 printf ("%d ns\n", b & 0x0F);
738 break;
739 case 0xA:
740 puts ("25 ns\n");
741 break;
742 case 0xB:
743 puts ("33 ns\n");
744 break;
745 case 0xC:
746 puts ("66 ns\n");
747 break;
748 case 0xD:
749 puts ("75 ns\n");
750 break;
751 default:
752 puts ("?? ns\n");
753 break;
754 }
755 }
757 static void decode_bits (u_char const b, char const *str[], int const do_once)
758 {
759 u_char mask;
761 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
762 if (b & mask) {
763 puts (*str);
764 if (do_once)
765 return;
766 }
767 }
768 }
770 /*
771 * Syntax:
772 * i2c sdram {i2c_chip}
773 */
774 static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
775 {
776 enum { unknown, EDO, SDRAM, DDR2 } type;
778 u_char chip;
779 u_char data[128];
780 u_char cksum;
781 int j;
783 static const char *decode_CAS_DDR2[] = {
784 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
785 };
787 static const char *decode_CAS_default[] = {
788 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
789 };
791 static const char *decode_CS_WE_default[] = {
792 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
793 };
795 static const char *decode_byte21_default[] = {
796 " TBD (bit 7)\n",
797 " Redundant row address\n",
798 " Differential clock input\n",
799 " Registerd DQMB inputs\n",
800 " Buffered DQMB inputs\n",
801 " On-card PLL\n",
802 " Registered address/control lines\n",
803 " Buffered address/control lines\n"
804 };
806 static const char *decode_byte22_DDR2[] = {
807 " TBD (bit 7)\n",
808 " TBD (bit 6)\n",
809 " TBD (bit 5)\n",
810 " TBD (bit 4)\n",
811 " TBD (bit 3)\n",
812 " Supports partial array self refresh\n",
813 " Supports 50 ohm ODT\n",
814 " Supports weak driver\n"
815 };
817 static const char *decode_row_density_DDR2[] = {
818 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
819 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
820 };
822 static const char *decode_row_density_default[] = {
823 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
824 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
825 };
827 if (argc < 2)
828 return CMD_RET_USAGE;
830 /*
831 * Chip is always specified.
832 */
833 chip = simple_strtoul (argv[1], NULL, 16);
835 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
836 puts ("No SDRAM Serial Presence Detect found.\n");
837 return 1;
838 }
840 cksum = 0;
841 for (j = 0; j < 63; j++) {
842 cksum += data[j];
843 }
844 if (cksum != data[63]) {
845 printf ("WARNING: Configuration data checksum failure:\n"
846 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
847 }
848 printf ("SPD data revision %d.%d\n",
849 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
850 printf ("Bytes used 0x%02X\n", data[0]);
851 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
853 puts ("Memory type ");
854 switch (data[2]) {
855 case 2:
856 type = EDO;
857 puts ("EDO\n");
858 break;
859 case 4:
860 type = SDRAM;
861 puts ("SDRAM\n");
862 break;
863 case 8:
864 type = DDR2;
865 puts ("DDR2\n");
866 break;
867 default:
868 type = unknown;
869 puts ("unknown\n");
870 break;
871 }
873 puts ("Row address bits ");
874 if ((data[3] & 0x00F0) == 0)
875 printf ("%d\n", data[3] & 0x0F);
876 else
877 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
879 puts ("Column address bits ");
880 if ((data[4] & 0x00F0) == 0)
881 printf ("%d\n", data[4] & 0x0F);
882 else
883 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
885 switch (type) {
886 case DDR2:
887 printf ("Number of ranks %d\n",
888 (data[5] & 0x07) + 1);
889 break;
890 default:
891 printf ("Module rows %d\n", data[5]);
892 break;
893 }
895 switch (type) {
896 case DDR2:
897 printf ("Module data width %d bits\n", data[6]);
898 break;
899 default:
900 printf ("Module data width %d bits\n",
901 (data[7] << 8) | data[6]);
902 break;
903 }
905 puts ("Interface signal levels ");
906 switch(data[8]) {
907 case 0: puts ("TTL 5.0 V\n"); break;
908 case 1: puts ("LVTTL\n"); break;
909 case 2: puts ("HSTL 1.5 V\n"); break;
910 case 3: puts ("SSTL 3.3 V\n"); break;
911 case 4: puts ("SSTL 2.5 V\n"); break;
912 case 5: puts ("SSTL 1.8 V\n"); break;
913 default: puts ("unknown\n"); break;
914 }
916 switch (type) {
917 case DDR2:
918 printf ("SDRAM cycle time ");
919 print_ddr2_tcyc (data[9]);
920 break;
921 default:
922 printf ("SDRAM cycle time %d.%d ns\n",
923 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
924 break;
925 }
927 switch (type) {
928 case DDR2:
929 printf ("SDRAM access time 0.%d%d ns\n",
930 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
931 break;
932 default:
933 printf ("SDRAM access time %d.%d ns\n",
934 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
935 break;
936 }
938 puts ("EDC configuration ");
939 switch (data[11]) {
940 case 0: puts ("None\n"); break;
941 case 1: puts ("Parity\n"); break;
942 case 2: puts ("ECC\n"); break;
943 default: puts ("unknown\n"); break;
944 }
946 if ((data[12] & 0x80) == 0)
947 puts ("No self refresh, rate ");
948 else
949 puts ("Self refresh, rate ");
951 switch(data[12] & 0x7F) {
952 case 0: puts ("15.625 us\n"); break;
953 case 1: puts ("3.9 us\n"); break;
954 case 2: puts ("7.8 us\n"); break;
955 case 3: puts ("31.3 us\n"); break;
956 case 4: puts ("62.5 us\n"); break;
957 case 5: puts ("125 us\n"); break;
958 default: puts ("unknown\n"); break;
959 }
961 switch (type) {
962 case DDR2:
963 printf ("SDRAM width (primary) %d\n", data[13]);
964 break;
965 default:
966 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
967 if ((data[13] & 0x80) != 0) {
968 printf (" (second bank) %d\n",
969 2 * (data[13] & 0x7F));
970 }
971 break;
972 }
974 switch (type) {
975 case DDR2:
976 if (data[14] != 0)
977 printf ("EDC width %d\n", data[14]);
978 break;
979 default:
980 if (data[14] != 0) {
981 printf ("EDC width %d\n",
982 data[14] & 0x7F);
984 if ((data[14] & 0x80) != 0) {
985 printf (" (second bank) %d\n",
986 2 * (data[14] & 0x7F));
987 }
988 }
989 break;
990 }
992 if (DDR2 != type) {
993 printf ("Min clock delay, back-to-back random column addresses "
994 "%d\n", data[15]);
995 }
997 puts ("Burst length(s) ");
998 if (data[16] & 0x80) puts (" Page");
999 if (data[16] & 0x08) puts (" 8");
1000 if (data[16] & 0x04) puts (" 4");
1001 if (data[16] & 0x02) puts (" 2");
1002 if (data[16] & 0x01) puts (" 1");
1003 putc ('\n');
1004 printf ("Number of banks %d\n", data[17]);
1006 switch (type) {
1007 case DDR2:
1008 puts ("CAS latency(s) ");
1009 decode_bits (data[18], decode_CAS_DDR2, 0);
1010 putc ('\n');
1011 break;
1012 default:
1013 puts ("CAS latency(s) ");
1014 decode_bits (data[18], decode_CAS_default, 0);
1015 putc ('\n');
1016 break;
1017 }
1019 if (DDR2 != type) {
1020 puts ("CS latency(s) ");
1021 decode_bits (data[19], decode_CS_WE_default, 0);
1022 putc ('\n');
1023 }
1025 if (DDR2 != type) {
1026 puts ("WE latency(s) ");
1027 decode_bits (data[20], decode_CS_WE_default, 0);
1028 putc ('\n');
1029 }
1031 switch (type) {
1032 case DDR2:
1033 puts ("Module attributes:\n");
1034 if (data[21] & 0x80)
1035 puts (" TBD (bit 7)\n");
1036 if (data[21] & 0x40)
1037 puts (" Analysis probe installed\n");
1038 if (data[21] & 0x20)
1039 puts (" TBD (bit 5)\n");
1040 if (data[21] & 0x10)
1041 puts (" FET switch external enable\n");
1042 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
1043 if (data[20] & 0x11) {
1044 printf (" %d active registers on DIMM\n",
1045 (data[21] & 0x03) + 1);
1046 }
1047 break;
1048 default:
1049 puts ("Module attributes:\n");
1050 if (!data[21])
1051 puts (" (none)\n");
1052 else
1053 decode_bits (data[21], decode_byte21_default, 0);
1054 break;
1055 }
1057 switch (type) {
1058 case DDR2:
1059 decode_bits (data[22], decode_byte22_DDR2, 0);
1060 break;
1061 default:
1062 puts ("Device attributes:\n");
1063 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1064 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1065 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1066 else puts (" Upper Vcc tolerance 10%\n");
1067 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1068 else puts (" Lower Vcc tolerance 10%\n");
1069 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1070 if (data[22] & 0x04) puts (" Supports precharge all\n");
1071 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1072 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1073 break;
1074 }
1076 switch (type) {
1077 case DDR2:
1078 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1079 print_ddr2_tcyc (data[23]);
1080 break;
1081 default:
1082 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1083 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
1084 break;
1085 }
1087 switch (type) {
1088 case DDR2:
1089 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1090 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1091 break;
1092 default:
1093 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1094 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1095 break;
1096 }
1098 switch (type) {
1099 case DDR2:
1100 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1101 print_ddr2_tcyc (data[25]);
1102 break;
1103 default:
1104 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1105 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
1106 break;
1107 }
1109 switch (type) {
1110 case DDR2:
1111 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1112 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1113 break;
1114 default:
1115 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1116 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1117 break;
1118 }
1120 switch (type) {
1121 case DDR2:
1122 printf ("Minimum row precharge %d.%02d ns\n",
1123 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
1124 break;
1125 default:
1126 printf ("Minimum row precharge %d ns\n", data[27]);
1127 break;
1128 }
1130 switch (type) {
1131 case DDR2:
1132 printf ("Row active to row active min %d.%02d ns\n",
1133 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
1134 break;
1135 default:
1136 printf ("Row active to row active min %d ns\n", data[28]);
1137 break;
1138 }
1140 switch (type) {
1141 case DDR2:
1142 printf ("RAS to CAS delay min %d.%02d ns\n",
1143 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
1144 break;
1145 default:
1146 printf ("RAS to CAS delay min %d ns\n", data[29]);
1147 break;
1148 }
1150 printf ("Minimum RAS pulse width %d ns\n", data[30]);
1152 switch (type) {
1153 case DDR2:
1154 puts ("Density of each row ");
1155 decode_bits (data[31], decode_row_density_DDR2, 1);
1156 putc ('\n');
1157 break;
1158 default:
1159 puts ("Density of each row ");
1160 decode_bits (data[31], decode_row_density_default, 1);
1161 putc ('\n');
1162 break;
1163 }
1165 switch (type) {
1166 case DDR2:
1167 puts ("Command and Address setup ");
1168 if (data[32] >= 0xA0) {
1169 printf ("1.%d%d ns\n",
1170 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
1171 } else {
1172 printf ("0.%d%d ns\n",
1173 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
1174 }
1175 break;
1176 default:
1177 printf ("Command and Address setup %c%d.%d ns\n",
1178 (data[32] & 0x80) ? '-' : '+',
1179 (data[32] >> 4) & 0x07, data[32] & 0x0F);
1180 break;
1181 }
1183 switch (type) {
1184 case DDR2:
1185 puts ("Command and Address hold ");
1186 if (data[33] >= 0xA0) {
1187 printf ("1.%d%d ns\n",
1188 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
1189 } else {
1190 printf ("0.%d%d ns\n",
1191 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
1192 }
1193 break;
1194 default:
1195 printf ("Command and Address hold %c%d.%d ns\n",
1196 (data[33] & 0x80) ? '-' : '+',
1197 (data[33] >> 4) & 0x07, data[33] & 0x0F);
1198 break;
1199 }
1201 switch (type) {
1202 case DDR2:
1203 printf ("Data signal input setup 0.%d%d ns\n",
1204 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
1205 break;
1206 default:
1207 printf ("Data signal input setup %c%d.%d ns\n",
1208 (data[34] & 0x80) ? '-' : '+',
1209 (data[34] >> 4) & 0x07, data[34] & 0x0F);
1210 break;
1211 }
1213 switch (type) {
1214 case DDR2:
1215 printf ("Data signal input hold 0.%d%d ns\n",
1216 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
1217 break;
1218 default:
1219 printf ("Data signal input hold %c%d.%d ns\n",
1220 (data[35] & 0x80) ? '-' : '+',
1221 (data[35] >> 4) & 0x07, data[35] & 0x0F);
1222 break;
1223 }
1225 puts ("Manufacturer's JEDEC ID ");
1226 for (j = 64; j <= 71; j++)
1227 printf ("%02X ", data[j]);
1228 putc ('\n');
1229 printf ("Manufacturing Location %02X\n", data[72]);
1230 puts ("Manufacturer's Part Number ");
1231 for (j = 73; j <= 90; j++)
1232 printf ("%02X ", data[j]);
1233 putc ('\n');
1234 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1235 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
1236 puts ("Assembly Serial Number ");
1237 for (j = 95; j <= 98; j++)
1238 printf ("%02X ", data[j]);
1239 putc ('\n');
1241 if (DDR2 != type) {
1242 printf ("Speed rating PC%d\n",
1243 data[126] == 0x66 ? 66 : data[126]);
1244 }
1245 return 0;
1246 }
1247 #endif
1249 #if defined(CONFIG_I2C_MUX)
1250 static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1251 {
1252 int ret=0;
1254 if (argc == 1) {
1255 /* show all busses */
1256 I2C_MUX *mux;
1257 I2C_MUX_DEVICE *device = i2c_mux_devices;
1259 printf ("Busses reached over muxes:\n");
1260 while (device != NULL) {
1261 printf ("Bus ID: %x\n", device->busid);
1262 printf (" reached over Mux(es):\n");
1263 mux = device->mux;
1264 while (mux != NULL) {
1265 printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
1266 mux = mux->next;
1267 }
1268 device = device->next;
1269 }
1270 } else {
1271 (void)i2c_mux_ident_muxstring ((uchar *)argv[1]);
1272 ret = 0;
1273 }
1274 return ret;
1275 }
1276 #endif /* CONFIG_I2C_MUX */
1278 #if defined(CONFIG_I2C_MULTI_BUS)
1279 static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1280 {
1281 int bus_idx, ret=0;
1283 if (argc == 1)
1284 /* querying current setting */
1285 printf("Current bus is %d\n", i2c_get_bus_num());
1286 else {
1287 bus_idx = simple_strtoul(argv[1], NULL, 10);
1288 printf("Setting bus to %d\n", bus_idx);
1289 ret = i2c_set_bus_num(bus_idx);
1290 if (ret)
1291 printf("Failure changing bus number (%d)\n", ret);
1292 }
1293 return ret;
1294 }
1295 #endif /* CONFIG_I2C_MULTI_BUS */
1297 static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1298 {
1299 int speed, ret=0;
1301 if (argc == 1)
1302 /* querying current speed */
1303 printf("Current bus speed=%d\n", i2c_get_bus_speed());
1304 else {
1305 speed = simple_strtoul(argv[1], NULL, 10);
1306 printf("Setting bus speed to %d Hz\n", speed);
1307 ret = i2c_set_bus_speed(speed);
1308 if (ret)
1309 printf("Failure changing bus speed (%d)\n", ret);
1310 }
1311 return ret;
1312 }
1314 static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1315 {
1316 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1317 }
1319 static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1320 {
1321 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1322 }
1324 static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1325 {
1326 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1327 return 0;
1328 }
1330 static cmd_tbl_t cmd_i2c_sub[] = {
1331 #if defined(CONFIG_I2C_MUX)
1332 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
1333 #endif /* CONFIG_I2C_MUX */
1334 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
1335 #if defined(CONFIG_I2C_MULTI_BUS)
1336 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
1337 #endif /* CONFIG_I2C_MULTI_BUS */
1338 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1339 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1340 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1341 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1342 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1343 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
1344 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
1345 U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""),
1346 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
1347 #if defined(CONFIG_CMD_SDRAM)
1348 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
1349 #endif
1350 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1351 };
1353 #ifdef CONFIG_NEEDS_MANUAL_RELOC
1354 void i2c_reloc(void) {
1355 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1356 }
1357 #endif
1359 static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1360 {
1361 cmd_tbl_t *c;
1363 if (argc < 2)
1364 return CMD_RET_USAGE;
1366 /* Strip off leading 'i2c' command argument */
1367 argc--;
1368 argv++;
1370 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1372 if (c)
1373 return c->cmd(cmdtp, flag, argc, argv);
1374 else
1375 return CMD_RET_USAGE;
1376 }
1378 /***************************************************/
1380 U_BOOT_CMD(
1381 i2c, 6, 1, do_i2c,
1382 "I2C sub-system",
1383 #if defined(CONFIG_I2C_MUX)
1384 "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
1385 #endif /* CONFIG_I2C_MUX */
1386 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
1387 #if defined(CONFIG_I2C_MULTI_BUS)
1388 "i2c dev [dev] - show or set current I2C bus\n"
1389 #endif /* CONFIG_I2C_MULTI_BUS */
1390 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
1391 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1392 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1393 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1394 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
1395 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
1396 "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
1397 "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
1398 "i2c reset - re-init the I2C Controller\n"
1399 #if defined(CONFIG_CMD_SDRAM)
1400 "i2c sdram chip - print SDRAM configuration information\n"
1401 #endif
1402 "i2c speed [speed] - show or set I2C bus speed"
1403 );
1405 #if defined(CONFIG_I2C_MUX)
1406 static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
1407 {
1408 I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
1410 if (i2c_mux_devices == NULL) {
1411 i2c_mux_devices = dev;
1412 return 0;
1413 }
1414 while (devtmp->next != NULL)
1415 devtmp = devtmp->next;
1417 devtmp->next = dev;
1418 return 0;
1419 }
1421 I2C_MUX_DEVICE *i2c_mux_search_device(int id)
1422 {
1423 I2C_MUX_DEVICE *device = i2c_mux_devices;
1425 while (device != NULL) {
1426 if (device->busid == id)
1427 return device;
1428 device = device->next;
1429 }
1430 return NULL;
1431 }
1433 /* searches in the buf from *pos the next ':'.
1434 * returns:
1435 * 0 if found (with *pos = where)
1436 * < 0 if an error occured
1437 * > 0 if the end of buf is reached
1438 */
1439 static int i2c_mux_search_next (int *pos, uchar *buf, int len)
1440 {
1441 while ((buf[*pos] != ':') && (*pos < len)) {
1442 *pos += 1;
1443 }
1444 if (*pos >= len)
1445 return 1;
1446 if (buf[*pos] != ':')
1447 return -1;
1448 return 0;
1449 }
1451 static int i2c_mux_get_busid (void)
1452 {
1453 int tmp = i2c_mux_busid;
1455 i2c_mux_busid ++;
1456 return tmp;
1457 }
1459 /* Analyses a Muxstring and immediately sends the
1460 commands to the muxes. Runs from flash.
1461 */
1462 int i2c_mux_ident_muxstring_f (uchar *buf)
1463 {
1464 int pos = 0;
1465 int oldpos;
1466 int ret = 0;
1467 int len = strlen((char *)buf);
1468 int chip;
1469 uchar channel;
1470 int was = 0;
1472 while (ret == 0) {
1473 oldpos = pos;
1474 /* search name */
1475 ret = i2c_mux_search_next(&pos, buf, len);
1476 if (ret != 0)
1477 printf ("ERROR\n");
1478 /* search address */
1479 pos ++;
1480 oldpos = pos;
1481 ret = i2c_mux_search_next(&pos, buf, len);
1482 if (ret != 0)
1483 printf ("ERROR\n");
1484 buf[pos] = 0;
1485 chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1486 buf[pos] = ':';
1487 /* search channel */
1488 pos ++;
1489 oldpos = pos;
1490 ret = i2c_mux_search_next(&pos, buf, len);
1491 if (ret < 0)
1492 printf ("ERROR\n");
1493 was = 0;
1494 if (buf[pos] != 0) {
1495 buf[pos] = 0;
1496 was = 1;
1497 }
1498 channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1499 if (was)
1500 buf[pos] = ':';
1501 if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
1502 printf ("Error setting Mux: chip:%x channel: \
1503 %x\n", chip, channel);
1504 return -1;
1505 }
1506 pos ++;
1507 oldpos = pos;
1509 }
1510 i2c_init_board();
1512 return 0;
1513 }
1515 /* Analyses a Muxstring and if this String is correct
1516 * adds a new I2C Bus.
1517 */
1518 I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
1519 {
1520 I2C_MUX_DEVICE *device;
1521 I2C_MUX *mux;
1522 int pos = 0;
1523 int oldpos;
1524 int ret = 0;
1525 int len = strlen((char *)buf);
1526 int was = 0;
1528 device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
1529 device->mux = NULL;
1530 device->busid = i2c_mux_get_busid ();
1531 device->next = NULL;
1532 while (ret == 0) {
1533 mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
1534 mux->next = NULL;
1535 /* search name of mux */
1536 oldpos = pos;
1537 ret = i2c_mux_search_next(&pos, buf, len);
1538 if (ret != 0)
1539 printf ("%s no name.\n", __FUNCTION__);
1540 mux->name = (char *)malloc (pos - oldpos + 1);
1541 memcpy (mux->name, &buf[oldpos], pos - oldpos);
1542 mux->name[pos - oldpos] = 0;
1543 /* search address */
1544 pos ++;
1545 oldpos = pos;
1546 ret = i2c_mux_search_next(&pos, buf, len);
1547 if (ret != 0)
1548 printf ("%s no mux address.\n", __FUNCTION__);
1549 buf[pos] = 0;
1550 mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1551 buf[pos] = ':';
1552 /* search channel */
1553 pos ++;
1554 oldpos = pos;
1555 ret = i2c_mux_search_next(&pos, buf, len);
1556 if (ret < 0)
1557 printf ("%s no mux channel.\n", __FUNCTION__);
1558 was = 0;
1559 if (buf[pos] != 0) {
1560 buf[pos] = 0;
1561 was = 1;
1562 }
1563 mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1564 if (was)
1565 buf[pos] = ':';
1566 if (device->mux == NULL)
1567 device->mux = mux;
1568 else {
1569 I2C_MUX *muxtmp = device->mux;
1570 while (muxtmp->next != NULL) {
1571 muxtmp = muxtmp->next;
1572 }
1573 muxtmp->next = mux;
1574 }
1575 pos ++;
1576 oldpos = pos;
1577 }
1578 if (ret > 0) {
1579 /* Add Device */
1580 i2c_mux_add_device (device);
1581 return device;
1582 }
1584 return NULL;
1585 }
1587 int i2x_mux_select_mux(int bus)
1588 {
1589 I2C_MUX_DEVICE *dev;
1590 I2C_MUX *mux;
1592 if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
1593 /* select Default Mux Bus */
1594 #if defined(CONFIG_SYS_I2C_IVM_BUS)
1595 i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
1596 #else
1597 {
1598 unsigned char *buf;
1599 buf = (unsigned char *) getenv("EEprom_ivm");
1600 if (buf != NULL)
1601 i2c_mux_ident_muxstring_f (buf);
1602 }
1603 #endif
1604 return 0;
1605 }
1606 dev = i2c_mux_search_device(bus);
1607 if (dev == NULL)
1608 return -1;
1610 mux = dev->mux;
1611 while (mux != NULL) {
1612 /* do deblocking on each level of mux, before mux config */
1613 i2c_init_board();
1614 if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
1615 printf ("Error setting Mux: chip:%x channel: \
1616 %x\n", mux->chip, mux->channel);
1617 return -1;
1618 }
1619 mux = mux->next;
1620 }
1621 /* do deblocking on each level of mux and after mux config */
1622 i2c_init_board();
1623 return 0;
1624 }
1625 #endif /* CONFIG_I2C_MUX */