drivers/mmc/bfin_sdh.c

   1 /*
   2  * Driver for Blackfin on-chip SDH controller
   3  *
   4  * Copyright (c) 2008-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <part.h>
  12 #include <mmc.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/errno.h>
  16 #include <asm/byteorder.h>
  17 #include <asm/blackfin.h>
  18 #include <asm/portmux.h>
  19 #include <asm/mach-common/bits/sdh.h>
  20 #include <asm/mach-common/bits/dma.h>
  21
  22 #if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__)
  23 # define bfin_read_SDH_CLK_CTL          bfin_read_RSI_CLK_CONTROL
  24 # define bfin_write_SDH_CLK_CTL         bfin_write_RSI_CLK_CONTROL
  25 # define bfin_write_SDH_ARGUMENT        bfin_write_RSI_ARGUMENT
  26 # define bfin_write_SDH_COMMAND         bfin_write_RSI_COMMAND
  27 # define bfin_read_SDH_RESPONSE0        bfin_read_RSI_RESPONSE0
  28 # define bfin_read_SDH_RESPONSE1        bfin_read_RSI_RESPONSE1
  29 # define bfin_read_SDH_RESPONSE2        bfin_read_RSI_RESPONSE2
  30 # define bfin_read_SDH_RESPONSE3        bfin_read_RSI_RESPONSE3
  31 # define bfin_write_SDH_DATA_TIMER      bfin_write_RSI_DATA_TIMER
  32 # define bfin_write_SDH_DATA_LGTH       bfin_write_RSI_DATA_LGTH
  33 # define bfin_read_SDH_DATA_CTL         bfin_read_RSI_DATA_CONTROL
  34 # define bfin_write_SDH_DATA_CTL        bfin_write_RSI_DATA_CONTROL
  35 # define bfin_read_SDH_STATUS           bfin_read_RSI_STATUS
  36 # define bfin_write_SDH_STATUS_CLR      bfin_write_RSI_STATUSCL
  37 # define bfin_read_SDH_CFG              bfin_read_RSI_CONFIG
  38 # define bfin_write_SDH_CFG             bfin_write_RSI_CONFIG
  39 # if defined(__ADSPBF60x__)
  40 # define bfin_read_SDH_BLK_SIZE         bfin_read_RSI_BLKSZ
  41 # define bfin_write_SDH_BLK_SIZE        bfin_write_RSI_BLKSZ
  42 # define bfin_write_DMA_START_ADDR      bfin_write_DMA10_START_ADDR
  43 # define bfin_write_DMA_X_COUNT         bfin_write_DMA10_X_COUNT
  44 # define bfin_write_DMA_X_MODIFY        bfin_write_DMA10_X_MODIFY
  45 # define bfin_write_DMA_CONFIG          bfin_write_DMA10_CONFIG
  46 # else
  47 # define bfin_read_SDH_PWR_CTL          bfin_read_RSI_PWR_CONTROL
  48 # define bfin_write_SDH_PWR_CTL         bfin_write_RSI_PWR_CONTROL
  49 # define bfin_write_DMA_START_ADDR      bfin_write_DMA4_START_ADDR
  50 # define bfin_write_DMA_X_COUNT         bfin_write_DMA4_X_COUNT
  51 # define bfin_write_DMA_X_MODIFY        bfin_write_DMA4_X_MODIFY
  52 # define bfin_write_DMA_CONFIG          bfin_write_DMA4_CONFIG
  53 # endif
  54 # define PORTMUX_PINS \
  55         { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
  56 #elif defined(__ADSPBF54x__)
  57 # define bfin_write_DMA_START_ADDR      bfin_write_DMA22_START_ADDR
  58 # define bfin_write_DMA_X_COUNT         bfin_write_DMA22_X_COUNT
  59 # define bfin_write_DMA_X_MODIFY        bfin_write_DMA22_X_MODIFY
  60 # define bfin_write_DMA_CONFIG          bfin_write_DMA22_CONFIG
  61 # define PORTMUX_PINS \
  62         { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
  63 #else
  64 # error no support for this proc yet
  65 #endif
  66
  67 static int
  68 sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
  69 {
  70         unsigned int status, timeout;
  71         int cmd = mmc_cmd->cmdidx;
  72         int flags = mmc_cmd->resp_type;
  73         int arg = mmc_cmd->cmdarg;
  74         int ret;
  75         u16 sdh_cmd;
  76
  77         sdh_cmd = cmd | CMD_E;
  78         if (flags & MMC_RSP_PRESENT)
  79                 sdh_cmd |= CMD_RSP;
  80         if (flags & MMC_RSP_136)
  81                 sdh_cmd |= CMD_L_RSP;
  82 #ifdef RSI_BLKSZ
  83         sdh_cmd |= CMD_DATA0_BUSY;
  84 #endif
  85
  86         bfin_write_SDH_ARGUMENT(arg);
  87         bfin_write_SDH_COMMAND(sdh_cmd);
  88
  89         /* wait for a while */
  90         timeout = 0;
  91         do {
  92                 if (++timeout > 1000000) {
  93                         status = CMD_TIME_OUT;
  94                         break;
  95                 }
  96                 udelay(1);
  97                 status = bfin_read_SDH_STATUS();
  98         } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
  99                 CMD_CRC_FAIL)));
 100
 101         if (flags & MMC_RSP_PRESENT) {
 102                 mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
 103                 if (flags & MMC_RSP_136) {
 104                         mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
 105                         mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
 106                         mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
 107                 }
 108         }
 109
 110         if (status & CMD_TIME_OUT)
 111                 ret = TIMEOUT;
 112         else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
 113                 ret = COMM_ERR;
 114         else
 115                 ret = 0;
 116
 117         bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
 118                                 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
 119 #ifdef RSI_BLKSZ
 120         /* wait till card ready */
 121         while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY))
 122                 continue;
 123         bfin_write_RSI_ESTAT(SD_CARD_READY);
 124 #endif
 125
 126         return ret;
 127 }
 128
 129 /* set data for single block transfer */
 130 static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
 131 {
 132         u16 data_ctl = 0;
 133         u16 dma_cfg = 0;
 134         unsigned long data_size = data->blocksize * data->blocks;
 135
 136         /* Don't support write yet. */
 137         if (data->flags & MMC_DATA_WRITE)
 138                 return UNUSABLE_ERR;
 139 #ifndef RSI_BLKSZ
 140         data_ctl |= ((ffs(data_size) - 1) << 4);
 141 #else
 142         bfin_write_SDH_BLK_SIZE(data_size);
 143 #endif
 144         data_ctl |= DTX_DIR;
 145         bfin_write_SDH_DATA_CTL(data_ctl);
 146         dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN;
 147
 148         bfin_write_SDH_DATA_TIMER(-1);
 149
 150         blackfin_dcache_flush_invalidate_range(data->dest,
 151                         data->dest + data_size);
 152         /* configure DMA */
 153         bfin_write_DMA_START_ADDR(data->dest);
 154         bfin_write_DMA_X_COUNT(data_size / 4);
 155         bfin_write_DMA_X_MODIFY(4);
 156         bfin_write_DMA_CONFIG(dma_cfg);
 157         bfin_write_SDH_DATA_LGTH(data_size);
 158         /* kick off transfer */
 159         bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
 160
 161         return 0;
 162 }
 163
 164
 165 static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
 166                 struct mmc_data *data)
 167 {
 168         u32 status;
 169         int ret = 0;
 170
 171         if (data) {
 172                 ret = sdh_setup_data(mmc, data);
 173                 if (ret)
 174                         return ret;
 175         }
 176
 177         ret = sdh_send_cmd(mmc, cmd);
 178         if (ret) {
 179                 bfin_write_SDH_COMMAND(0);
 180                 bfin_write_DMA_CONFIG(0);
 181                 bfin_write_SDH_DATA_CTL(0);
 182                 SSYNC();
 183                 printf("sending CMD%d failed\n", cmd->cmdidx);
 184                 return ret;
 185         }
 186
 187         if (data) {
 188                 do {
 189                         udelay(1);
 190                         status = bfin_read_SDH_STATUS();
 191                 } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
 192
 193                 if (status & DAT_TIME_OUT) {
 194                         bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
 195                         ret |= TIMEOUT;
 196                 } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
 197                         bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
 198                         ret |= COMM_ERR;
 199                 } else
 200                         bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
 201
 202                 if (ret) {
 203                         printf("tranfering data failed\n");
 204                         return ret;
 205                 }
 206         }
 207         return 0;
 208 }
 209
 210 static void sdh_set_clk(unsigned long clk)
 211 {
 212         unsigned long sys_clk;
 213         unsigned long clk_div;
 214         u16 clk_ctl = 0;
 215
 216         clk_ctl = bfin_read_SDH_CLK_CTL();
 217         if (clk) {
 218                 /* setting SD_CLK */
 219                 sys_clk = get_sclk();
 220                 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
 221                 if (sys_clk % (2 * clk) == 0)
 222                         clk_div = sys_clk / (2 * clk) - 1;
 223                 else
 224                         clk_div = sys_clk / (2 * clk);
 225
 226                 if (clk_div > 0xff)
 227                         clk_div = 0xff;
 228                 clk_ctl |= (clk_div & 0xff);
 229                 clk_ctl |= CLK_E;
 230                 bfin_write_SDH_CLK_CTL(clk_ctl);
 231         } else
 232                 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
 233 }
 234
 235 static void bfin_sdh_set_ios(struct mmc *mmc)
 236 {
 237         u16 cfg = 0;
 238         u16 clk_ctl = 0;
 239
 240         if (mmc->bus_width == 4) {
 241                 cfg = bfin_read_SDH_CFG();
 242 #ifndef RSI_BLKSZ
 243                 cfg &= ~PD_SDDAT3;
 244 #endif
 245                 cfg |= PUP_SDDAT3;
 246                 bfin_write_SDH_CFG(cfg);
 247                 clk_ctl |= WIDE_BUS_4;
 248         }
 249         bfin_write_SDH_CLK_CTL(clk_ctl);
 250         sdh_set_clk(mmc->clock);
 251 }
 252
 253 static int bfin_sdh_init(struct mmc *mmc)
 254 {
 255         const unsigned short pins[] = PORTMUX_PINS;
 256         int ret;
 257
 258         /* Initialize sdh controller */
 259         ret = peripheral_request_list(pins, "bfin_sdh");
 260         if (ret < 0)
 261                 return ret;
 262 #if defined(__ADSPBF54x__)
 263         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 264 #endif
 265         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 266         /* Disable card detect pin */
 267         bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
 268 #ifndef RSI_BLKSZ
 269         bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL);
 270 #else
 271         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON);
 272 #endif
 273         return 0;
 274 }
 275
 276
 277 int bfin_mmc_init(bd_t *bis)
 278 {
 279         struct mmc *mmc = NULL;
 280
 281         mmc = malloc(sizeof(struct mmc));
 282
 283         if (!mmc)
 284                 return -ENOMEM;
 285         sprintf(mmc->name, "Blackfin SDH");
 286         mmc->send_cmd = bfin_sdh_request;
 287         mmc->set_ios = bfin_sdh_set_ios;
 288         mmc->init = bfin_sdh_init;
 289         mmc->getcd = NULL;
 290         mmc->host_caps = MMC_MODE_4BIT;
 291
 292         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 293         mmc->f_max = get_sclk();
 294         mmc->f_min = mmc->f_max >> 9;
 295
 296         mmc->b_max = 0;
 297
 298         mmc_register(mmc);
 299
 300         return 0;
 301 }