ARM: OMAP4+: Make control module register structure generic
[glsdk/glsdk-u-boot.git] / drivers / mmc / omap_hsmmc.c
1 /*
2  * (C) Copyright 2008
3  * Texas Instruments, <www.ti.com>
4  * Sukumar Ghorai <s-ghorai@ti.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation's version 2 of
12  * the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
25 #include <config.h>
26 #include <common.h>
27 #include <mmc.h>
28 #include <part.h>
29 #include <i2c.h>
30 #include <twl4030.h>
31 #include <twl6030.h>
32 #include <twl6035.h>
33 #include <asm/gpio.h>
34 #include <asm/io.h>
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
38 /* common definitions for all OMAPs */
39 #define SYSCTL_SRC      (1 << 25)
40 #define SYSCTL_SRD      (1 << 26)
42 struct omap_hsmmc_data {
43         struct hsmmc *base_addr;
44         int cd_gpio;
45         int wp_gpio;
46 };
48 /* If we fail after 1 second wait, something is really bad */
49 #define MAX_RETRY_MS    1000
51 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
52 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
53                         unsigned int siz);
54 static struct mmc hsmmc_dev[3];
55 static struct omap_hsmmc_data hsmmc_dev_data[3];
57 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
58         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
59 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
60 {
61         if (!gpio_is_valid(gpio))
62                 return -1;
64         if (gpio_request(gpio, label) < 0)
65                 return -1;
67         if (gpio_direction_input(gpio) < 0)
68                 return -1;
70         return gpio;
71 }
73 static int omap_mmc_getcd(struct mmc *mmc)
74 {
75         int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
76         return gpio_get_value(cd_gpio);
77 }
79 static int omap_mmc_getwp(struct mmc *mmc)
80 {
81         int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio;
82         return gpio_get_value(wp_gpio);
83 }
84 #else
85 static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
86 {
87         return -1;
88 }
90 #define omap_mmc_getcd NULL
91 #define omap_mmc_getwp NULL
92 #endif
94 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
95 static void omap4_vmmc_pbias_config(struct mmc *mmc)
96 {
97         u32 value = 0;
99         value = readl((*ctrl)->control_pbiaslite);
100         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
101         writel(value, (*ctrl)->control_pbiaslite);
102         /* set VMMC to 3V */
103         twl6030_power_mmc_init();
104         value = readl((*ctrl)->control_pbiaslite);
105         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
106         writel(value, (*ctrl)->control_pbiaslite);
108 #endif
110 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
111 static void omap5_pbias_config(struct mmc *mmc)
113         u32 value = 0;
115         value = readl((*ctrl)->control_pbias);
116         value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
117         value |= SDCARD_BIAS_HIZ_MODE;
118         writel(value, (*ctrl)->control_pbias);
120         twl6035_mmc1_poweron_ldo();
122         value = readl((*ctrl)->control_pbias);
123         value &= ~SDCARD_BIAS_HIZ_MODE;
124         value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
125         writel(value, (*ctrl)->control_pbias);
127         value = readl((*ctrl)->control_pbias);
128         if (value & (1 << 23)) {
129                 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
130                 value |= SDCARD_BIAS_HIZ_MODE;
131                 writel(value, (*ctrl)->control_pbias);
132         }
134 #endif
136 unsigned char mmc_board_init(struct mmc *mmc)
138 #if defined(CONFIG_OMAP34XX)
139         t2_t *t2_base = (t2_t *)T2_BASE;
140         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
141         u32 pbias_lite;
143         pbias_lite = readl(&t2_base->pbias_lite);
144         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
145         writel(pbias_lite, &t2_base->pbias_lite);
146 #endif
147 #if defined(CONFIG_TWL4030_POWER)
148         twl4030_power_mmc_init();
149         mdelay(100);    /* ramp-up delay from Linux code */
150 #endif
151 #if defined(CONFIG_OMAP34XX)
152         writel(pbias_lite | PBIASLITEPWRDNZ1 |
153                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
154                 &t2_base->pbias_lite);
156         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
157                 &t2_base->devconf0);
159         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
160                 &t2_base->devconf1);
162         /* Change from default of 52MHz to 26MHz if necessary */
163         if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
164                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
165                         &t2_base->ctl_prog_io1);
167         writel(readl(&prcm_base->fclken1_core) |
168                 EN_MMC1 | EN_MMC2 | EN_MMC3,
169                 &prcm_base->fclken1_core);
171         writel(readl(&prcm_base->iclken1_core) |
172                 EN_MMC1 | EN_MMC2 | EN_MMC3,
173                 &prcm_base->iclken1_core);
174 #endif
176 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
177         /* PBIAS config needed for MMC1 only */
178         if (mmc->block_dev.dev == 0)
179                 omap4_vmmc_pbias_config(mmc);
180 #endif
181 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
182         if (mmc->block_dev.dev == 0)
183                 omap5_pbias_config(mmc);
184 #endif
186         return 0;
189 void mmc_init_stream(struct hsmmc *mmc_base)
191         ulong start;
193         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
195         writel(MMC_CMD0, &mmc_base->cmd);
196         start = get_timer(0);
197         while (!(readl(&mmc_base->stat) & CC_MASK)) {
198                 if (get_timer(0) - start > MAX_RETRY_MS) {
199                         printf("%s: timedout waiting for cc!\n", __func__);
200                         return;
201                 }
202         }
203         writel(CC_MASK, &mmc_base->stat)
204                 ;
205         writel(MMC_CMD0, &mmc_base->cmd)
206                 ;
207         start = get_timer(0);
208         while (!(readl(&mmc_base->stat) & CC_MASK)) {
209                 if (get_timer(0) - start > MAX_RETRY_MS) {
210                         printf("%s: timedout waiting for cc2!\n", __func__);
211                         return;
212                 }
213         }
214         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
218 static int mmc_init_setup(struct mmc *mmc)
220         struct hsmmc *mmc_base;
221         unsigned int reg_val;
222         unsigned int dsor;
223         ulong start;
225         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
226         mmc_board_init(mmc);
228         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
229                 &mmc_base->sysconfig);
230         start = get_timer(0);
231         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
232                 if (get_timer(0) - start > MAX_RETRY_MS) {
233                         printf("%s: timedout waiting for cc2!\n", __func__);
234                         return TIMEOUT;
235                 }
236         }
237         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
238         start = get_timer(0);
239         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
240                 if (get_timer(0) - start > MAX_RETRY_MS) {
241                         printf("%s: timedout waiting for softresetall!\n",
242                                 __func__);
243                         return TIMEOUT;
244                 }
245         }
246         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
247         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
248                 &mmc_base->capa);
250         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
252         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
253                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
254                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
256         dsor = 240;
257         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
258                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
259         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
260                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
261         start = get_timer(0);
262         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
263                 if (get_timer(0) - start > MAX_RETRY_MS) {
264                         printf("%s: timedout waiting for ics!\n", __func__);
265                         return TIMEOUT;
266                 }
267         }
268         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
270         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
272         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
273                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
274                 &mmc_base->ie);
276         mmc_init_stream(mmc_base);
278         return 0;
281 /*
282  * MMC controller internal finite state machine reset
283  *
284  * Used to reset command or data internal state machines, using respectively
285  * SRC or SRD bit of SYSCTL register
286  */
287 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
289         ulong start;
291         mmc_reg_out(&mmc_base->sysctl, bit, bit);
293         start = get_timer(0);
294         while ((readl(&mmc_base->sysctl) & bit) != 0) {
295                 if (get_timer(0) - start > MAX_RETRY_MS) {
296                         printf("%s: timedout waiting for sysctl %x to clear\n",
297                                 __func__, bit);
298                         return;
299                 }
300         }
303 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
304                         struct mmc_data *data)
306         struct hsmmc *mmc_base;
307         unsigned int flags, mmc_stat;
308         ulong start;
310         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
311         start = get_timer(0);
312         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
313                 if (get_timer(0) - start > MAX_RETRY_MS) {
314                         printf("%s: timedout waiting on cmd inhibit to clear\n",
315                                         __func__);
316                         return TIMEOUT;
317                 }
318         }
319         writel(0xFFFFFFFF, &mmc_base->stat);
320         start = get_timer(0);
321         while (readl(&mmc_base->stat)) {
322                 if (get_timer(0) - start > MAX_RETRY_MS) {
323                         printf("%s: timedout waiting for STAT (%x) to clear\n",
324                                 __func__, readl(&mmc_base->stat));
325                         return TIMEOUT;
326                 }
327         }
328         /*
329          * CMDREG
330          * CMDIDX[13:8] : Command index
331          * DATAPRNT[5]  : Data Present Select
332          * ENCMDIDX[4]  : Command Index Check Enable
333          * ENCMDCRC[3]  : Command CRC Check Enable
334          * RSPTYP[1:0]
335          *      00 = No Response
336          *      01 = Length 136
337          *      10 = Length 48
338          *      11 = Length 48 Check busy after response
339          */
340         /* Delay added before checking the status of frq change
341          * retry not supported by mmc.c(core file)
342          */
343         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
344                 udelay(50000); /* wait 50 ms */
346         if (!(cmd->resp_type & MMC_RSP_PRESENT))
347                 flags = 0;
348         else if (cmd->resp_type & MMC_RSP_136)
349                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
350         else if (cmd->resp_type & MMC_RSP_BUSY)
351                 flags = RSP_TYPE_LGHT48B;
352         else
353                 flags = RSP_TYPE_LGHT48;
355         /* enable default flags */
356         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
357                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
359         if (cmd->resp_type & MMC_RSP_CRC)
360                 flags |= CCCE_CHECK;
361         if (cmd->resp_type & MMC_RSP_OPCODE)
362                 flags |= CICE_CHECK;
364         if (data) {
365                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
366                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
367                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
368                         data->blocksize = 512;
369                         writel(data->blocksize | (data->blocks << 16),
370                                                         &mmc_base->blk);
371                 } else
372                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
374                 if (data->flags & MMC_DATA_READ)
375                         flags |= (DP_DATA | DDIR_READ);
376                 else
377                         flags |= (DP_DATA | DDIR_WRITE);
378         }
380         writel(cmd->cmdarg, &mmc_base->arg);
381         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
383         start = get_timer(0);
384         do {
385                 mmc_stat = readl(&mmc_base->stat);
386                 if (get_timer(0) - start > MAX_RETRY_MS) {
387                         printf("%s : timeout: No status update\n", __func__);
388                         return TIMEOUT;
389                 }
390         } while (!mmc_stat);
392         if ((mmc_stat & IE_CTO) != 0) {
393                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
394                 return TIMEOUT;
395         } else if ((mmc_stat & ERRI_MASK) != 0)
396                 return -1;
398         if (mmc_stat & CC_MASK) {
399                 writel(CC_MASK, &mmc_base->stat);
400                 if (cmd->resp_type & MMC_RSP_PRESENT) {
401                         if (cmd->resp_type & MMC_RSP_136) {
402                                 /* response type 2 */
403                                 cmd->response[3] = readl(&mmc_base->rsp10);
404                                 cmd->response[2] = readl(&mmc_base->rsp32);
405                                 cmd->response[1] = readl(&mmc_base->rsp54);
406                                 cmd->response[0] = readl(&mmc_base->rsp76);
407                         } else
408                                 /* response types 1, 1b, 3, 4, 5, 6 */
409                                 cmd->response[0] = readl(&mmc_base->rsp10);
410                 }
411         }
413         if (data && (data->flags & MMC_DATA_READ)) {
414                 mmc_read_data(mmc_base, data->dest,
415                                 data->blocksize * data->blocks);
416         } else if (data && (data->flags & MMC_DATA_WRITE)) {
417                 mmc_write_data(mmc_base, data->src,
418                                 data->blocksize * data->blocks);
419         }
420         return 0;
423 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
425         unsigned int *output_buf = (unsigned int *)buf;
426         unsigned int mmc_stat;
427         unsigned int count;
429         /*
430          * Start Polled Read
431          */
432         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
433         count /= 4;
435         while (size) {
436                 ulong start = get_timer(0);
437                 do {
438                         mmc_stat = readl(&mmc_base->stat);
439                         if (get_timer(0) - start > MAX_RETRY_MS) {
440                                 printf("%s: timedout waiting for status!\n",
441                                                 __func__);
442                                 return TIMEOUT;
443                         }
444                 } while (mmc_stat == 0);
446                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
447                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
449                 if ((mmc_stat & ERRI_MASK) != 0)
450                         return 1;
452                 if (mmc_stat & BRR_MASK) {
453                         unsigned int k;
455                         writel(readl(&mmc_base->stat) | BRR_MASK,
456                                 &mmc_base->stat);
457                         for (k = 0; k < count; k++) {
458                                 *output_buf = readl(&mmc_base->data);
459                                 output_buf++;
460                         }
461                         size -= (count*4);
462                 }
464                 if (mmc_stat & BWR_MASK)
465                         writel(readl(&mmc_base->stat) | BWR_MASK,
466                                 &mmc_base->stat);
468                 if (mmc_stat & TC_MASK) {
469                         writel(readl(&mmc_base->stat) | TC_MASK,
470                                 &mmc_base->stat);
471                         break;
472                 }
473         }
474         return 0;
477 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
478                                 unsigned int size)
480         unsigned int *input_buf = (unsigned int *)buf;
481         unsigned int mmc_stat;
482         unsigned int count;
484         /*
485          * Start Polled Read
486          */
487         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
488         count /= 4;
490         while (size) {
491                 ulong start = get_timer(0);
492                 do {
493                         mmc_stat = readl(&mmc_base->stat);
494                         if (get_timer(0) - start > MAX_RETRY_MS) {
495                                 printf("%s: timedout waiting for status!\n",
496                                                 __func__);
497                                 return TIMEOUT;
498                         }
499                 } while (mmc_stat == 0);
501                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
502                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
504                 if ((mmc_stat & ERRI_MASK) != 0)
505                         return 1;
507                 if (mmc_stat & BWR_MASK) {
508                         unsigned int k;
510                         writel(readl(&mmc_base->stat) | BWR_MASK,
511                                         &mmc_base->stat);
512                         for (k = 0; k < count; k++) {
513                                 writel(*input_buf, &mmc_base->data);
514                                 input_buf++;
515                         }
516                         size -= (count*4);
517                 }
519                 if (mmc_stat & BRR_MASK)
520                         writel(readl(&mmc_base->stat) | BRR_MASK,
521                                 &mmc_base->stat);
523                 if (mmc_stat & TC_MASK) {
524                         writel(readl(&mmc_base->stat) | TC_MASK,
525                                 &mmc_base->stat);
526                         break;
527                 }
528         }
529         return 0;
532 static void mmc_set_ios(struct mmc *mmc)
534         struct hsmmc *mmc_base;
535         unsigned int dsor = 0;
536         ulong start;
538         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
539         /* configue bus width */
540         switch (mmc->bus_width) {
541         case 8:
542                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
543                         &mmc_base->con);
544                 break;
546         case 4:
547                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
548                         &mmc_base->con);
549                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
550                         &mmc_base->hctl);
551                 break;
553         case 1:
554         default:
555                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
556                         &mmc_base->con);
557                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
558                         &mmc_base->hctl);
559                 break;
560         }
562         /* configure clock with 96Mhz system clock.
563          */
564         if (mmc->clock != 0) {
565                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
566                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
567                         dsor++;
568         }
570         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
571                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
573         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
574                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
576         start = get_timer(0);
577         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
578                 if (get_timer(0) - start > MAX_RETRY_MS) {
579                         printf("%s: timedout waiting for ics!\n", __func__);
580                         return;
581                 }
582         }
583         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
586 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
587                 int wp_gpio)
589         struct mmc *mmc = &hsmmc_dev[dev_index];
590         struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
592         sprintf(mmc->name, "OMAP SD/MMC");
593         mmc->send_cmd = mmc_send_cmd;
594         mmc->set_ios = mmc_set_ios;
595         mmc->init = mmc_init_setup;
596         mmc->getcd = omap_mmc_getcd;
597         mmc->getwp = omap_mmc_getwp;
598         mmc->priv = priv_data;
600         switch (dev_index) {
601         case 0:
602                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
603                 break;
604 #ifdef OMAP_HSMMC2_BASE
605         case 1:
606                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
607                 break;
608 #endif
609 #ifdef OMAP_HSMMC3_BASE
610         case 2:
611                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
612                 break;
613 #endif
614         default:
615                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
616                 return 1;
617         }
618         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
619         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
620         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
621         mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
622                                 MMC_MODE_HC) & ~host_caps_mask;
624         mmc->f_min = 400000;
626         if (f_max != 0)
627                 mmc->f_max = f_max;
628         else {
629                 if (mmc->host_caps & MMC_MODE_HS) {
630                         if (mmc->host_caps & MMC_MODE_HS_52MHz)
631                                 mmc->f_max = 52000000;
632                         else
633                                 mmc->f_max = 26000000;
634                 } else
635                         mmc->f_max = 20000000;
636         }
638         mmc->b_max = 0;
640 #if defined(CONFIG_OMAP34XX)
641         /*
642          * Silicon revs 2.1 and older do not support multiblock transfers.
643          */
644         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
645                 mmc->b_max = 1;
646 #endif
648         mmc_register(mmc);
650         return 0;