1 /*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
20 #include <common.h>
21 #include <malloc.h>
22 #include <sdhci.h>
23 #include <asm/arch/mmc.h>
24 #include <asm/arch/clk.h>
26 static char *S5P_NAME = "SAMSUNG SDHCI";
27 static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
28 {
29 unsigned long val, ctrl;
30 /*
31 * SELCLKPADDS[17:16]
32 * 00 = 2mA
33 * 01 = 4mA
34 * 10 = 7mA
35 * 11 = 9mA
36 */
37 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
39 val = sdhci_readl(host, SDHCI_CONTROL2);
40 val &= SDHCI_CTRL2_SELBASECLK_SHIFT;
42 val |= SDHCI_CTRL2_ENSTAASYNCCLR |
43 SDHCI_CTRL2_ENCMDCNFMSK |
44 SDHCI_CTRL2_ENFBCLKRX |
45 SDHCI_CTRL2_ENCLKOUTHOLD;
47 sdhci_writel(host, val, SDHCI_CONTROL2);
49 /*
50 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
51 * FCSel[1:0] : Rx Feedback Clock Delay Control
52 * Inverter delay means10ns delay if SDCLK 50MHz setting
53 * 01 = Delay1 (basic delay)
54 * 11 = Delay2 (basic delay + 2ns)
55 * 00 = Delay3 (inverter delay)
56 * 10 = Delay4 (inverter delay + 2ns)
57 */
58 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
59 sdhci_writel(host, val, SDHCI_CONTROL3);
61 /*
62 * SELBASECLK[5:4]
63 * 00/01 = HCLK
64 * 10 = EPLL
65 * 11 = XTI or XEXTCLK
66 */
67 ctrl = sdhci_readl(host, SDHCI_CONTROL2);
68 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
69 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
70 sdhci_writel(host, ctrl, SDHCI_CONTROL2);
71 }
73 int s5p_sdhci_init(u32 regbase, int index, int bus_width)
74 {
75 struct sdhci_host *host = NULL;
76 host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
77 if (!host) {
78 printf("sdhci__host malloc fail!\n");
79 return 1;
80 }
82 host->name = S5P_NAME;
83 host->ioaddr = (void *)regbase;
85 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
86 SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
87 SDHCI_QUIRK_WAIT_SEND_CMD;
88 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
89 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
91 host->set_control_reg = &s5p_sdhci_set_control_reg;
92 host->set_clock = set_mmc_clk;
93 host->index = index;
95 host->host_caps = MMC_MODE_HC;
97 add_sdhci(host, 52000000, 400000);
98 return 0;
99 }