e9e0b24f74d7552808e3bb949cfe77bea95015a3
1 /*
2 * SPI flash interface
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
6 *
7 * Licensed under the GPL-2 or later.
8 */
10 #include <common.h>
11 #include <fdtdec.h>
12 #include <malloc.h>
13 #include <spi.h>
14 #include <spi_flash.h>
15 #include <watchdog.h>
17 #include "spi_flash_internal.h"
19 DECLARE_GLOBAL_DATA_PTR;
21 static void spi_flash_addr(u32 addr, u8 *cmd)
22 {
23 /* cmd[0] is actual command */
24 cmd[1] = addr >> 16;
25 cmd[2] = addr >> 8;
26 cmd[3] = addr >> 0;
27 }
29 static int spi_flash_read_write(struct spi_slave *spi,
30 const u8 *cmd, size_t cmd_len,
31 const u8 *data_out, u8 *data_in,
32 size_t data_len)
33 {
34 unsigned long flags = SPI_XFER_BEGIN;
35 int ret;
37 if (data_len == 0)
38 flags |= SPI_XFER_END;
40 ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
41 if (ret) {
42 debug("SF: Failed to send command (%zu bytes): %d\n",
43 cmd_len, ret);
44 } else if (data_len != 0) {
45 ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END);
46 if (ret)
47 debug("SF: Failed to transfer %zu bytes of data: %d\n",
48 data_len, ret);
49 }
51 return ret;
52 }
54 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
55 {
56 return spi_flash_cmd_read(spi, &cmd, 1, response, len);
57 }
59 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
60 size_t cmd_len, void *data, size_t data_len)
61 {
62 return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
63 }
65 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
66 const void *data, size_t data_len)
67 {
68 return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
69 }
71 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
72 {
73 struct spi_slave *spi = flash->spi;
74 unsigned long timebase;
75 int ret;
76 u8 status;
77 u8 check_status = 0x0;
78 u8 poll_bit = STATUS_WIP;
79 u8 cmd = flash->poll_cmd;
81 if (cmd == CMD_FLAG_STATUS) {
82 poll_bit = STATUS_PEC;
83 check_status = poll_bit;
84 }
86 ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
87 if (ret) {
88 debug("SF: fail to read %s status register\n",
89 cmd == CMD_READ_STATUS ? "read" : "flag");
90 return ret;
91 }
93 timebase = get_timer(0);
94 do {
95 WATCHDOG_RESET();
97 ret = spi_xfer(spi, 8, NULL, &status, 0);
98 if (ret)
99 return -1;
101 if ((status & poll_bit) == check_status)
102 break;
104 } while (get_timer(timebase) < timeout);
106 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
108 if ((status & poll_bit) == check_status)
109 return 0;
111 /* Timed out */
112 debug("SF: time out!\n");
113 return -1;
114 }
116 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
117 size_t cmd_len, const void *buf, size_t buf_len)
118 {
119 struct spi_slave *spi = flash->spi;
120 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
121 int ret;
123 if (buf == NULL)
124 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
126 ret = spi_claim_bus(flash->spi);
127 if (ret) {
128 debug("SF: unable to claim SPI bus\n");
129 return ret;
130 }
132 ret = spi_flash_cmd_write_enable(flash);
133 if (ret < 0) {
134 debug("SF: enabling write failed\n");
135 return ret;
136 }
138 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
139 if (ret < 0) {
140 debug("SF: write cmd failed\n");
141 return ret;
142 }
144 ret = spi_flash_cmd_wait_ready(flash, timeout);
145 if (ret < 0) {
146 debug("SF: write %s timed out\n",
147 timeout == SPI_FLASH_PROG_TIMEOUT ?
148 "program" : "page erase");
149 return ret;
150 }
152 spi_release_bus(spi);
154 return ret;
155 }
157 int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
158 {
159 u32 erase_size;
160 u8 cmd[4];
161 int ret = -1;
163 erase_size = flash->sector_size;
164 if (offset % erase_size || len % erase_size) {
165 debug("SF: Erase offset/length not multiple of erase size\n");
166 return -1;
167 }
169 if (erase_size == 4096)
170 cmd[0] = CMD_ERASE_4K;
171 else
172 cmd[0] = CMD_ERASE_64K;
174 while (len) {
175 #ifdef CONFIG_SPI_FLASH_BAR
176 u8 bank_sel;
178 bank_sel = offset / SPI_FLASH_16MB_BOUN;
180 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
181 if (ret) {
182 debug("SF: fail to set bank%d\n", bank_sel);
183 return ret;
184 }
185 #endif
186 spi_flash_addr(offset, cmd);
188 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
189 cmd[2], cmd[3], offset);
191 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
192 if (ret < 0) {
193 debug("SF: erase failed\n");
194 break;
195 }
197 offset += erase_size;
198 len -= erase_size;
199 }
201 return ret;
202 }
204 int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
205 size_t len, const void *buf)
206 {
207 unsigned long byte_addr, page_size;
208 size_t chunk_len, actual;
209 u8 cmd[4];
210 int ret = -1;
212 page_size = flash->page_size;
214 cmd[0] = CMD_PAGE_PROGRAM;
215 for (actual = 0; actual < len; actual += chunk_len) {
216 #ifdef CONFIG_SPI_FLASH_BAR
217 u8 bank_sel;
219 bank_sel = offset / SPI_FLASH_16MB_BOUN;
221 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
222 if (ret) {
223 debug("SF: fail to set bank%d\n", bank_sel);
224 return ret;
225 }
226 #endif
227 byte_addr = offset % page_size;
228 chunk_len = min(len - actual, page_size - byte_addr);
230 if (flash->spi->max_write_size)
231 chunk_len = min(chunk_len, flash->spi->max_write_size);
233 spi_flash_addr(offset, cmd);
235 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
236 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
238 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
239 buf + actual, chunk_len);
240 if (ret < 0) {
241 debug("SF: write failed\n");
242 break;
243 }
245 offset += chunk_len;
246 }
248 return ret;
249 }
251 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
252 size_t cmd_len, void *data, size_t data_len)
253 {
254 struct spi_slave *spi = flash->spi;
255 int ret;
257 ret = spi_claim_bus(flash->spi);
258 if (ret) {
259 debug("SF: unable to claim SPI bus\n");
260 return ret;
261 }
263 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
264 if (ret < 0) {
265 debug("SF: read cmd failed\n");
266 return ret;
267 }
269 spi_release_bus(spi);
271 return ret;
272 }
274 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
275 size_t len, void *data)
276 {
277 u8 cmd[5], bank_sel = 0;
278 u32 remain_len, read_len;
279 int ret = -1;
281 /* Handle memory-mapped SPI */
282 if (flash->memory_map)
283 memcpy(data, flash->memory_map + offset, len);
285 cmd[0] = CMD_READ_ARRAY_FAST;
286 cmd[4] = 0x00;
288 while (len) {
289 #ifdef CONFIG_SPI_FLASH_BAR
290 bank_sel = offset / SPI_FLASH_16MB_BOUN;
292 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
293 if (ret) {
294 debug("SF: fail to set bank%d\n", bank_sel);
295 return ret;
296 }
297 #endif
298 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
299 if (len < remain_len)
300 read_len = len;
301 else
302 read_len = remain_len;
304 spi_flash_addr(offset, cmd);
306 ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
307 data, read_len);
308 if (ret < 0) {
309 debug("SF: read failed\n");
310 break;
311 }
313 offset += read_len;
314 len -= read_len;
315 data += read_len;
316 }
318 return ret;
319 }
321 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
322 {
323 u8 cmd;
324 int ret;
326 cmd = CMD_WRITE_STATUS;
327 ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
328 if (ret < 0) {
329 debug("SF: fail to write status register\n");
330 return ret;
331 }
333 return 0;
334 }
336 #ifdef CONFIG_SPI_FLASH_BAR
337 int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
338 {
339 u8 cmd;
340 int ret;
342 if (flash->bank_curr == bank_sel) {
343 debug("SF: not require to enable bank%d\n", bank_sel);
344 return 0;
345 }
347 cmd = flash->bank_write_cmd;
348 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
349 if (ret < 0) {
350 debug("SF: fail to write bank register\n");
351 return ret;
352 }
353 flash->bank_curr = bank_sel;
355 return 0;
356 }
358 int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
359 {
360 u8 cmd;
361 u8 curr_bank = 0;
363 /* discover bank cmds */
364 switch (idcode0) {
365 case SPI_FLASH_SPANSION_IDCODE0:
366 flash->bank_read_cmd = CMD_BANKADDR_BRRD;
367 flash->bank_write_cmd = CMD_BANKADDR_BRWR;
368 break;
369 case SPI_FLASH_STMICRO_IDCODE0:
370 case SPI_FLASH_WINBOND_IDCODE0:
371 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
372 flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
373 break;
374 default:
375 printf("SF: Unsupported bank commands %02x\n", idcode0);
376 return -1;
377 }
379 /* read the bank reg - on which bank the flash is in currently */
380 cmd = flash->bank_read_cmd;
381 if (flash->size > SPI_FLASH_16MB_BOUN) {
382 if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) {
383 debug("SF: fail to read bank addr register\n");
384 return -1;
385 }
386 flash->bank_curr = curr_bank;
387 } else {
388 flash->bank_curr = curr_bank;
389 }
391 return 0;
392 }
393 #endif
395 #ifdef CONFIG_OF_CONTROL
396 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
397 {
398 fdt_addr_t addr;
399 fdt_size_t size;
400 int node;
402 /* If there is no node, do nothing */
403 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
404 if (node < 0)
405 return 0;
407 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
408 if (addr == FDT_ADDR_T_NONE) {
409 debug("%s: Cannot decode address\n", __func__);
410 return 0;
411 }
413 if (flash->size != size) {
414 debug("%s: Memory map must cover entire device\n", __func__);
415 return -1;
416 }
417 flash->memory_map = (void *)addr;
419 return 0;
420 }
421 #endif /* CONFIG_OF_CONTROL */
423 /*
424 * The following table holds all device probe functions
425 *
426 * shift: number of continuation bytes before the ID
427 * idcode: the expected IDCODE or 0xff for non JEDEC devices
428 * probe: the function to call
429 *
430 * Non JEDEC devices should be ordered in the table such that
431 * the probe functions with best detection algorithms come first.
432 *
433 * Several matching entries are permitted, they will be tried
434 * in sequence until a probe function returns non NULL.
435 *
436 * IDCODE_CONT_LEN may be redefined if a device needs to declare a
437 * larger "shift" value. IDCODE_PART_LEN generally shouldn't be
438 * changed. This is the max number of bytes probe functions may
439 * examine when looking up part-specific identification info.
440 *
441 * Probe functions will be given the idcode buffer starting at their
442 * manu id byte (the "idcode" in the table below). In other words,
443 * all of the continuation bytes will be skipped (the "shift" below).
444 */
445 #define IDCODE_CONT_LEN 0
446 #define IDCODE_PART_LEN 5
447 static const struct {
448 const u8 shift;
449 const u8 idcode;
450 struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
451 } flashes[] = {
452 /* Keep it sorted by define name */
453 #ifdef CONFIG_SPI_FLASH_ATMEL
454 { 0, 0x1f, spi_flash_probe_atmel, },
455 #endif
456 #ifdef CONFIG_SPI_FLASH_EON
457 { 0, 0x1c, spi_flash_probe_eon, },
458 #endif
459 #ifdef CONFIG_SPI_FLASH_MACRONIX
460 { 0, 0xc2, spi_flash_probe_macronix, },
461 #endif
462 #ifdef CONFIG_SPI_FLASH_SPANSION
463 { 0, 0x01, spi_flash_probe_spansion, },
464 #endif
465 #ifdef CONFIG_SPI_FLASH_SST
466 { 0, 0xbf, spi_flash_probe_sst, },
467 #endif
468 #ifdef CONFIG_SPI_FLASH_STMICRO
469 { 0, 0x20, spi_flash_probe_stmicro, },
470 #endif
471 #ifdef CONFIG_SPI_FLASH_WINBOND
472 { 0, 0xef, spi_flash_probe_winbond, },
473 #endif
474 #ifdef CONFIG_SPI_FRAM_RAMTRON
475 { 6, 0xc2, spi_fram_probe_ramtron, },
476 # undef IDCODE_CONT_LEN
477 # define IDCODE_CONT_LEN 6
478 #endif
479 /* Keep it sorted by best detection */
480 #ifdef CONFIG_SPI_FLASH_STMICRO
481 { 0, 0xff, spi_flash_probe_stmicro, },
482 #endif
483 #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
484 { 0, 0xff, spi_fram_probe_ramtron, },
485 #endif
486 };
487 #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
489 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
490 unsigned int max_hz, unsigned int spi_mode)
491 {
492 struct spi_slave *spi;
493 struct spi_flash *flash = NULL;
494 int ret, i, shift;
495 u8 idcode[IDCODE_LEN], *idp;
497 spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
498 if (!spi) {
499 printf("SF: Failed to set up slave\n");
500 return NULL;
501 }
503 ret = spi_claim_bus(spi);
504 if (ret) {
505 debug("SF: Failed to claim SPI bus: %d\n", ret);
506 goto err_claim_bus;
507 }
509 /* Read the ID codes */
510 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
511 if (ret)
512 goto err_read_id;
514 #ifdef DEBUG
515 printf("SF: Got idcodes\n");
516 print_buffer(0, idcode, 1, sizeof(idcode), 0);
517 #endif
519 /* count the number of continuation bytes */
520 for (shift = 0, idp = idcode;
521 shift < IDCODE_CONT_LEN && *idp == 0x7f;
522 ++shift, ++idp)
523 continue;
525 /* search the table for matches in shift and id */
526 for (i = 0; i < ARRAY_SIZE(flashes); ++i)
527 if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
528 /* we have a match, call probe */
529 flash = flashes[i].probe(spi, idp);
530 if (flash)
531 break;
532 }
534 if (!flash) {
535 printf("SF: Unsupported manufacturer %02x\n", *idp);
536 goto err_manufacturer_probe;
537 }
539 #ifdef CONFIG_SPI_FLASH_BAR
540 /* Configure the BAR - disover bank cmds and read current bank */
541 ret = spi_flash_bank_config(flash, *idp);
542 if (ret < 0)
543 goto err_manufacturer_probe;
544 #endif
546 #ifdef CONFIG_OF_CONTROL
547 if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
548 debug("SF: FDT decode error\n");
549 goto err_manufacturer_probe;
550 }
551 #endif
552 printf("SF: Detected %s with page size ", flash->name);
553 print_size(flash->sector_size, ", total ");
554 print_size(flash->size, "");
555 if (flash->memory_map)
556 printf(", mapped at %p", flash->memory_map);
557 puts("\n");
558 #ifndef CONFIG_SPI_FLASH_BAR
559 if (flash->size > SPI_FLASH_16MB_BOUN) {
560 puts("SF: Warning - Only lower 16MiB accessible,");
561 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
562 }
563 #endif
565 spi_release_bus(spi);
567 return flash;
569 err_manufacturer_probe:
570 err_read_id:
571 spi_release_bus(spi);
572 err_claim_bus:
573 spi_free_slave(spi);
574 return NULL;
575 }
577 void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi,
578 const char *name)
579 {
580 struct spi_flash *flash;
581 void *ptr;
583 ptr = malloc(size);
584 if (!ptr) {
585 debug("SF: Failed to allocate memory\n");
586 return NULL;
587 }
588 memset(ptr, '\0', size);
589 flash = (struct spi_flash *)(ptr + offset);
591 /* Set up some basic fields - caller will sort out sizes */
592 flash->spi = spi;
593 flash->name = name;
594 flash->poll_cmd = CMD_READ_STATUS;
596 flash->read = spi_flash_cmd_read_fast;
597 flash->write = spi_flash_cmd_write_multi;
598 flash->erase = spi_flash_cmd_erase;
600 return flash;
601 }
603 void spi_flash_free(struct spi_flash *flash)
604 {
605 spi_free_slave(flash->spi);
606 free(flash);
607 }