1 /*
2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 /*
25 * board/config.h - configuration options, board specific
26 */
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
31 /*
32 * High Level Configuration Options
33 * (easy to change)
34 */
36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37 #define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */
39 #define CONFIG_SYS_TEXT_BASE 0x40000000
41 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
42 #define CONFIG_SYS_SMC_RXBUFLEN 128
43 #define CONFIG_SYS_MAXIDLE 10
44 #define CONFIG_BAUDRATE 115200
46 #define CONFIG_BOOTCOUNT_LIMIT
48 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
50 #define CONFIG_BOARD_TYPES 1 /* support board types */
52 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
54 #undef CONFIG_BOOTARGS
56 #define CONFIG_EXTRA_ENV_SETTINGS \
57 "netdev=eth0\0" \
58 "nfsargs=setenv bootargs root=/dev/nfs rw " \
59 "nfsroot=${serverip}:${rootpath}\0" \
60 "ramargs=setenv bootargs root=/dev/ram rw\0" \
61 "addip=setenv bootargs ${bootargs} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
63 ":${hostname}:${netdev}:off panic=1\0" \
64 "flash_nfs=run nfsargs addip;" \
65 "bootm ${kernel_addr}\0" \
66 "flash_self=run ramargs addip;" \
67 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
68 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
69 "rootpath=/opt/eldk/ppc_8xx\0" \
70 "hostname=FPS860L\0" \
71 "bootfile=FPS860L/uImage\0" \
72 "fdt_addr=40040000\0" \
73 "kernel_addr=40060000\0" \
74 "ramdisk_addr=40200000\0" \
75 "u-boot=FPS860L/u-image.bin\0" \
76 "load=tftp 200000 ${u-boot}\0" \
77 "update=prot off 40000000 +${filesize};" \
78 "era 40000000 +${filesize};" \
79 "cp.b 200000 40000000 ${filesize};" \
80 "sete filesize;save\0" \
81 ""
82 #define CONFIG_BOOTCOMMAND "run flash_self"
84 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
85 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
87 #undef CONFIG_WATCHDOG /* watchdog disabled */
89 /*
90 * BOOTP options
91 */
92 #define CONFIG_BOOTP_SUBNETMASK
93 #define CONFIG_BOOTP_GATEWAY
94 #define CONFIG_BOOTP_HOSTNAME
95 #define CONFIG_BOOTP_BOOTPATH
96 #define CONFIG_BOOTP_BOOTFILESIZE
97 #define CONFIG_BOOTP_SUBNETMASK
98 #define CONFIG_BOOTP_GATEWAY
99 #define CONFIG_BOOTP_HOSTNAME
100 #define CONFIG_BOOTP_NISDOMAIN
101 #define CONFIG_BOOTP_BOOTPATH
102 #define CONFIG_BOOTP_DNS
103 #define CONFIG_BOOTP_DNS2
104 #define CONFIG_BOOTP_SEND_HOSTNAME
105 #define CONFIG_BOOTP_NTPSERVER
106 #define CONFIG_BOOTP_TIMEOFFSET
108 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
110 /*
111 * Command line configuration.
112 */
113 #include <config_cmd_default.h>
115 #define CONFIG_CMD_ASKENV
116 #define CONFIG_CMD_DATE
117 #define CONFIG_CMD_DHCP
118 #define CONFIG_CMD_JFFS2
119 #define CONFIG_CMD_NFS
120 #define CONFIG_CMD_SNTP
123 #define CONFIG_NETCONSOLE
126 /*
127 * Miscellaneous configurable options
128 */
129 #define CONFIG_SYS_LONGHELP /* undef to save memory */
130 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
132 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
133 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
135 #if defined(CONFIG_CMD_KGDB)
136 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
137 #else
138 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
139 #endif
140 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
141 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
142 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
144 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
145 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
147 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
149 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
151 /*
152 * Low Level Configuration Settings
153 * (address mappings, register initial values, etc.)
154 * You should know what you are doing if you make changes here.
155 */
156 /*-----------------------------------------------------------------------
157 * Internal Memory Mapped Register
158 */
159 #define CONFIG_SYS_IMMR 0xFFF00000
161 /*-----------------------------------------------------------------------
162 * Definitions for initial stack pointer and data area (in DPRAM)
163 */
164 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
165 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
166 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
167 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
169 /*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
173 */
174 #define CONFIG_SYS_SDRAM_BASE 0x00000000
175 #define CONFIG_SYS_FLASH_BASE 0x40000000
176 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
177 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
178 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
180 /*
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
184 */
185 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
187 /*-----------------------------------------------------------------------
188 * FLASH organization
189 */
191 /* use CFI flash driver */
192 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
193 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
194 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
195 #define CONFIG_SYS_FLASH_EMPTY_INFO
196 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
197 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
198 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
200 #define CONFIG_ENV_IS_IN_FLASH 1
201 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
202 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
204 /* Address and size of Redundant Environment Sector */
205 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
206 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
208 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
210 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
212 /*-----------------------------------------------------------------------
213 * Dynamic MTD partition support
214 */
215 #define CONFIG_CMD_MTDPARTS
216 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
217 #define CONFIG_FLASH_CFI_MTD
218 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
220 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
221 "128k(dtb)," \
222 "1664k(kernel)," \
223 "2m(rootfs)," \
224 "4m(data)"
226 /*-----------------------------------------------------------------------
227 * Hardware Information Block
228 */
229 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
230 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
231 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
233 /*-----------------------------------------------------------------------
234 * Cache Configuration
235 */
236 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
237 #if defined(CONFIG_CMD_KGDB)
238 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
239 #endif
241 /*-----------------------------------------------------------------------
242 * SYPCR - System Protection Control 11-9
243 * SYPCR can only be written once after reset!
244 *-----------------------------------------------------------------------
245 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
246 */
247 #if defined(CONFIG_WATCHDOG)
248 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
249 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
250 #else
251 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
252 #endif
254 /*-----------------------------------------------------------------------
255 * SIUMCR - SIU Module Configuration 11-6
256 *-----------------------------------------------------------------------
257 * PCMCIA config., multi-function pin tri-state
258 */
259 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
261 /*-----------------------------------------------------------------------
262 * TBSCR - Time Base Status and Control 11-26
263 *-----------------------------------------------------------------------
264 * Clear Reference Interrupt Status, Timebase freezing enabled
265 */
266 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
268 /*-----------------------------------------------------------------------
269 * RTCSC - Real-Time Clock Status and Control Register 11-27
270 *-----------------------------------------------------------------------
271 */
272 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
274 /*-----------------------------------------------------------------------
275 * PISCR - Periodic Interrupt Status and Control 11-31
276 *-----------------------------------------------------------------------
277 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
278 */
279 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
281 /*-----------------------------------------------------------------------
282 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
283 *-----------------------------------------------------------------------
284 * Reset PLL lock status sticky bit, timer expired status bit and timer
285 * interrupt status bit - leave PLL multiplication factor unchanged !
286 */
287 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
289 /*-----------------------------------------------------------------------
290 * SCCR - System Clock and reset Control Register 15-27
291 *-----------------------------------------------------------------------
292 * Set clock output, timebase and RTC source and divider,
293 * power management and some other internal clocks
294 */
295 #define SCCR_MASK SCCR_EBDF11
296 #define CONFIG_SYS_SCCR (SCCR_TBS | \
297 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
298 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
299 SCCR_DFALCD00)
301 /*-----------------------------------------------------------------------
302 * PCMCIA stuff
303 *-----------------------------------------------------------------------
304 *
305 */
306 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
307 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
308 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
309 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
310 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
311 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
312 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
313 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
315 /*-----------------------------------------------------------------------
316 *
317 *-----------------------------------------------------------------------
318 *
319 */
320 #define CONFIG_SYS_DER 0
322 /*
323 * Init Memory Controller:
324 *
325 * BR0/1 and OR0/1 (FLASH)
326 */
328 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
329 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
331 /* used to re-map FLASH both when starting from SRAM or FLASH:
332 * restrict access enough to keep SRAM working (if any)
333 * but not too much to meddle with FLASH accesses
334 */
335 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
336 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
338 /*
339 * FLASH timing:
340 */
341 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
342 OR_SCY_3_CLK | OR_EHTR | OR_BI)
344 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
345 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
346 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
348 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
349 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
350 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
352 /*
353 * BR2/3 and OR2/3 (SDRAM)
354 *
355 */
356 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
357 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
358 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
360 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
361 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
363 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
364 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
366 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
367 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
369 /*
370 * Memory Periodic Timer Prescaler
371 *
372 * The Divider for PTA (refresh timer) configuration is based on an
373 * example SDRAM configuration (64 MBit, one bank). The adjustment to
374 * the number of chip selects (NCS) and the actually needed refresh
375 * rate is done by setting MPTPR.
376 *
377 * PTA is calculated from
378 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
379 *
380 * gclk CPU clock (not bus clock!)
381 * Trefresh Refresh cycle * 4 (four word bursts used)
382 *
383 * 4096 Rows from SDRAM example configuration
384 * 1000 factor s -> ms
385 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
386 * 4 Number of refresh cycles per period
387 * 64 Refresh cycle in ms per number of rows
388 * --------------------------------------------
389 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
390 *
391 * 50 MHz => 50.000.000 / Divider = 98
392 * 66 Mhz => 66.000.000 / Divider = 129
393 * 80 Mhz => 80.000.000 / Divider = 156
394 */
396 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
397 #define CONFIG_SYS_MAMR_PTA 98
399 /*
400 * For 16 MBit, refresh rates could be 31.3 us
401 * (= 64 ms / 2K = 125 / quad bursts).
402 * For a simpler initialization, 15.6 us is used instead.
403 *
404 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
405 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
406 */
407 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
408 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
410 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
411 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
412 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
414 /*
415 * MAMR settings for SDRAM
416 */
418 /* 8 column SDRAM */
419 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
420 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
421 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
422 /* 9 column SDRAM */
423 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
424 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
425 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
427 #define CONFIG_SCC1_ENET
429 /* pass open firmware flat tree */
430 #define CONFIG_OF_LIBFDT 1
431 #define CONFIG_OF_BOARD_SETUP 1
432 #define CONFIG_HWCONFIG 1
434 #endif /* __CONFIG_H */