1 /*
2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 /*
25 * board/config.h - configuration options, board specific
26 */
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
31 /*
32 * High Level Configuration Options
33 * (easy to change)
34 */
36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37 #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
38 #define CONFIG_NSCU 1
40 #define CONFIG_SYS_TEXT_BASE 0x40000000
42 #define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */
43 #define CONFIG_SYS_SMC_RXBUFLEN 128
44 #define CONFIG_SYS_MAXIDLE 10
46 #define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */
48 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52 #define CONFIG_BOARD_TYPES 1 /* support board types */
54 #define CONFIG_PREBOOT "echo;" \
55 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
56 "echo"
58 #undef CONFIG_BOOTARGS
60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "netdev=eth0\0" \
62 "nfsargs=setenv bootargs root=/dev/nfs rw " \
63 "nfsroot=${serverip}:${rootpath}\0" \
64 "ramargs=setenv bootargs root=/dev/ram rw\0" \
65 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \
68 "flash_nfs=run nfsargs addip;" \
69 "bootm ${kernel_addr}\0" \
70 "flash_self=run ramargs addip;" \
71 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
73 "rootpath=/opt/eldk/ppc_8xx\0" \
74 "hostname=NSCU\0" \
75 "bootfile=${hostname}/uImage\0" \
76 "kernel_addr=40080000\0" \
77 "ramdisk_addr=40180000\0" \
78 "u-boot=${hostname}/u-image.bin\0" \
79 "load=tftp 200000 ${u-boot}\0" \
80 "update=prot off 40000000 +${filesize};" \
81 "era 40000000 +${filesize};" \
82 "cp.b 200000 40000000 ${filesize};" \
83 "sete filesize;save\0" \
84 ""
85 #define CONFIG_BOOTCOMMAND "run flash_self"
87 #define CONFIG_MISC_INIT_R 1
89 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
90 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
92 #undef CONFIG_WATCHDOG /* watchdog disabled */
94 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
96 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
98 /*
99 * BOOTP options
100 */
101 #define CONFIG_BOOTP_SUBNETMASK
102 #define CONFIG_BOOTP_GATEWAY
103 #define CONFIG_BOOTP_HOSTNAME
104 #define CONFIG_BOOTP_BOOTPATH
105 #define CONFIG_BOOTP_BOOTFILESIZE
108 #define CONFIG_MAC_PARTITION
109 #define CONFIG_DOS_PARTITION
111 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
113 #define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */
116 /*
117 * Command line configuration.
118 */
119 #include <config_cmd_default.h>
121 #define CONFIG_CMD_ASKENV
122 #define CONFIG_CMD_DATE
123 #define CONFIG_CMD_DHCP
124 #define CONFIG_CMD_ELF
125 #define CONFIG_CMD_IDE
126 #define CONFIG_CMD_NFS
127 #define CONFIG_CMD_SNTP
130 #define CONFIG_NETCONSOLE
133 /*
134 * Miscellaneous configurable options
135 */
136 #define CONFIG_SYS_LONGHELP /* undef to save memory */
137 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
139 #define CONFIG_CMDLINE_EDITING 1 /* add command line history
140 */
141 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
143 #if defined(CONFIG_CMD_KGDB)
144 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
145 #else
146 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
147 #endif
148 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
152 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
153 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
155 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
157 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
159 /*
160 * Low Level Configuration Settings
161 * (address mappings, register initial values, etc.)
162 * You should know what you are doing if you make changes here.
163 */
164 /*-----------------------------------------------------------------------
165 * Internal Memory Mapped Register
166 */
167 #define CONFIG_SYS_IMMR 0xFFF00000
169 /*-----------------------------------------------------------------------
170 * Definitions for initial stack pointer and data area (in DPRAM)
171 */
172 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
173 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
174 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
177 /*-----------------------------------------------------------------------
178 * Start addresses for the final memory configuration
179 * (Set up by the startup code)
180 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
181 */
182 #define CONFIG_SYS_SDRAM_BASE 0x00000000
183 #define CONFIG_SYS_FLASH_BASE 0x40000000
184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
186 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
188 /*
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
192 */
193 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
195 /*-----------------------------------------------------------------------
196 * FLASH organization
197 */
199 /* use CFI flash driver */
200 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
201 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
202 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
203 #define CONFIG_SYS_FLASH_EMPTY_INFO
204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
206 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
208 #define CONFIG_ENV_IS_IN_FLASH 1
209 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
210 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
212 /* Address and size of Redundant Environment Sector */
213 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
214 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
216 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
218 /*-----------------------------------------------------------------------
219 * Hardware Information Block
220 */
221 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
222 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
223 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
225 /*-----------------------------------------------------------------------
226 * Cache Configuration
227 */
228 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
229 #if defined(CONFIG_CMD_KGDB)
230 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
231 #endif
233 /*-----------------------------------------------------------------------
234 * SYPCR - System Protection Control 11-9
235 * SYPCR can only be written once after reset!
236 *-----------------------------------------------------------------------
237 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
238 */
239 #if defined(CONFIG_WATCHDOG)
240 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
241 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
242 #else
243 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
244 #endif
246 /*-----------------------------------------------------------------------
247 * SIUMCR - SIU Module Configuration 11-6
248 *-----------------------------------------------------------------------
249 * PCMCIA config., multi-function pin tri-state
250 */
251 #ifndef CONFIG_CAN_DRIVER
252 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
253 #else /* we must activate GPL5 in the SIUMCR for CAN */
254 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
255 #endif /* CONFIG_CAN_DRIVER */
257 /*-----------------------------------------------------------------------
258 * TBSCR - Time Base Status and Control 11-26
259 *-----------------------------------------------------------------------
260 * Clear Reference Interrupt Status, Timebase freezing enabled
261 */
262 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
264 /*-----------------------------------------------------------------------
265 * RTCSC - Real-Time Clock Status and Control Register 11-27
266 *-----------------------------------------------------------------------
267 */
268 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
270 /*-----------------------------------------------------------------------
271 * PISCR - Periodic Interrupt Status and Control 11-31
272 *-----------------------------------------------------------------------
273 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
274 */
275 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
277 /*-----------------------------------------------------------------------
278 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
279 *-----------------------------------------------------------------------
280 * Reset PLL lock status sticky bit, timer expired status bit and timer
281 * interrupt status bit
282 */
283 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
285 /*-----------------------------------------------------------------------
286 * SCCR - System Clock and reset Control Register 15-27
287 *-----------------------------------------------------------------------
288 * Set clock output, timebase and RTC source and divider,
289 * power management and some other internal clocks
290 */
291 #define SCCR_MASK SCCR_EBDF11
292 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
293 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
294 SCCR_DFALCD00)
296 /*-----------------------------------------------------------------------
297 * PCMCIA stuff
298 *-----------------------------------------------------------------------
299 *
300 */
301 /* NSCU use both slots, SLOT_A as "primary". */
302 #define CONFIG_PCMCIA_SLOT_A 1
304 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
305 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
306 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
307 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
308 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
309 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
310 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
311 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
312 #define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */
313 #define PCMCIA_SOCKETS_NO 2 /* we have two sockets */
314 #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */
316 /*-----------------------------------------------------------------------
317 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
318 *-----------------------------------------------------------------------
319 */
321 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
322 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
324 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
325 #undef CONFIG_IDE_LED /* LED for ide not supported */
326 #undef CONFIG_IDE_RESET /* reset for ide not supported */
328 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE buses */
329 #define CONFIG_SYS_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */
331 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
332 #define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */
334 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
336 /* Offset for data I/O */
337 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
339 /* Offset for normal register accesses */
340 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
342 /* Offset for alternate registers */
343 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
345 /*-----------------------------------------------------------------------
346 *
347 *-----------------------------------------------------------------------
348 *
349 */
350 #define CONFIG_SYS_DER 0
352 /*
353 * Init Memory Controller:
354 *
355 * BR0/1 and OR0/1 (FLASH)
356 */
358 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
359 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
361 /* used to re-map FLASH both when starting from SRAM or FLASH:
362 * restrict access enough to keep SRAM working (if any)
363 * but not too much to meddle with FLASH accesses
364 */
365 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
366 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
368 /*
369 * FLASH timing:
370 */
371 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
372 OR_SCY_3_CLK | OR_EHTR | OR_BI)
374 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
375 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
376 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
378 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
379 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
380 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
382 /*
383 * BR2/3 and OR2/3 (SDRAM)
384 *
385 */
386 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
387 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
388 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
390 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
391 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
393 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
394 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
396 #ifndef CONFIG_CAN_DRIVER
397 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
398 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
399 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
400 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
401 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
402 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
403 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
404 BR_PS_8 | BR_MS_UPMB | BR_V )
405 #endif /* CONFIG_CAN_DRIVER */
407 #ifdef CONFIG_ISP1362_USB
408 #define CONFIG_SYS_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */
409 #define CONFIG_SYS_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */
410 #define CONFIG_SYS_OR5_ISP1362 (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \
411 OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK)
412 #define CONFIG_SYS_BR5_ISP1362 ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \
413 BR_PS_16 | BR_MS_GPCM | BR_V )
414 #endif /* CONFIG_ISP1362_USB */
416 /*
417 * Memory Periodic Timer Prescaler
418 *
419 * The Divider for PTA (refresh timer) configuration is based on an
420 * example SDRAM configuration (64 MBit, one bank). The adjustment to
421 * the number of chip selects (NCS) and the actually needed refresh
422 * rate is done by setting MPTPR.
423 *
424 * PTA is calculated from
425 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
426 *
427 * gclk CPU clock (not bus clock!)
428 * Trefresh Refresh cycle * 4 (four word bursts used)
429 *
430 * 4096 Rows from SDRAM example configuration
431 * 1000 factor s -> ms
432 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
433 * 4 Number of refresh cycles per period
434 * 64 Refresh cycle in ms per number of rows
435 * --------------------------------------------
436 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
437 *
438 * 50 MHz => 50.000.000 / Divider = 98
439 * 66 Mhz => 66.000.000 / Divider = 129
440 * 80 Mhz => 80.000.000 / Divider = 156
441 */
443 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
444 #define CONFIG_SYS_MAMR_PTA 98
446 /*
447 * For 16 MBit, refresh rates could be 31.3 us
448 * (= 64 ms / 2K = 125 / quad bursts).
449 * For a simpler initialization, 15.6 us is used instead.
450 *
451 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
452 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
453 */
454 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
455 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
457 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
458 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
459 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
461 /*
462 * MAMR settings for SDRAM
463 */
465 /* 8 column SDRAM */
466 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
467 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
468 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
469 /* 9 column SDRAM */
470 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
471 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
472 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474 #undef CONFIG_SCC1_ENET
475 #define CONFIG_FEC_ENET
477 /* pass open firmware flat tree */
478 #define CONFIG_OF_LIBFDT 1
479 #define CONFIG_OF_BOARD_SETUP 1
480 #define CONFIG_HWCONFIG 1
482 #endif /* __CONFIG_H */