1 /*
2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 /*
25 * board/config.h - configuration options, board specific
26 */
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
31 /*
32 * High Level Configuration Options
33 * (easy to change)
34 */
36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37 #define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
39 #define CONFIG_SYS_TEXT_BASE 0x40000000
41 #ifdef CONFIG_LCD /* with LCD controller ? */
42 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
43 #endif
45 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
46 #define CONFIG_SYS_SMC_RXBUFLEN 128
47 #define CONFIG_SYS_MAXIDLE 10
48 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
50 #define CONFIG_BOOTCOUNT_LIMIT
52 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
54 #define CONFIG_BOARD_TYPES 1 /* support board types */
56 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
58 #undef CONFIG_BOOTARGS
60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "netdev=eth0\0" \
62 "nfsargs=setenv bootargs root=/dev/nfs rw " \
63 "nfsroot=${serverip}:${rootpath}\0" \
64 "ramargs=setenv bootargs root=/dev/ram rw\0" \
65 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \
68 "flash_nfs=run nfsargs addip;" \
69 "bootm ${kernel_addr}\0" \
70 "flash_self=run ramargs addip;" \
71 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
73 "rootpath=/opt/eldk/ppc_8xx\0" \
74 "hostname=TQM823M\0" \
75 "bootfile=TQM823M/uImage\0" \
76 "fdt_addr=40080000\0" \
77 "kernel_addr=400A0000\0" \
78 "ramdisk_addr=40280000\0" \
79 "u-boot=TQM823M/u-image.bin\0" \
80 "load=tftp 200000 ${u-boot}\0" \
81 "update=prot off 40000000 +${filesize};" \
82 "era 40000000 +${filesize};" \
83 "cp.b 200000 40000000 ${filesize};" \
84 "sete filesize;save\0" \
85 ""
86 #define CONFIG_BOOTCOMMAND "run flash_self"
88 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
89 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
91 #undef CONFIG_WATCHDOG /* watchdog disabled */
93 #ifdef CONFIG_LCD
94 # undef CONFIG_STATUS_LED /* disturbs display */
95 #else
96 # define CONFIG_STATUS_LED 1 /* Status LED enabled */
97 #endif /* CONFIG_LCD */
99 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
101 /*
102 * BOOTP options
103 */
104 #define CONFIG_BOOTP_SUBNETMASK
105 #define CONFIG_BOOTP_GATEWAY
106 #define CONFIG_BOOTP_HOSTNAME
107 #define CONFIG_BOOTP_BOOTPATH
108 #define CONFIG_BOOTP_BOOTFILESIZE
111 #define CONFIG_MAC_PARTITION
112 #define CONFIG_DOS_PARTITION
114 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
117 /*
118 * Command line configuration.
119 */
120 #include <config_cmd_default.h>
122 #define CONFIG_CMD_ASKENV
123 #define CONFIG_CMD_DATE
124 #define CONFIG_CMD_DHCP
125 #define CONFIG_CMD_ELF
126 #define CONFIG_CMD_EXT2
127 #define CONFIG_CMD_IDE
128 #define CONFIG_CMD_JFFS2
129 #define CONFIG_CMD_NFS
130 #define CONFIG_CMD_SNTP
133 #define CONFIG_NETCONSOLE
136 /*
137 * Miscellaneous configurable options
138 */
139 #define CONFIG_SYS_LONGHELP /* undef to save memory */
140 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
142 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
143 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
145 #if defined(CONFIG_CMD_KGDB)
146 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
147 #else
148 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
149 #endif
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
154 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
155 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
157 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
159 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
161 /*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 */
166 /*-----------------------------------------------------------------------
167 * Internal Memory Mapped Register
168 */
169 #define CONFIG_SYS_IMMR 0xFFF00000
171 /*-----------------------------------------------------------------------
172 * Definitions for initial stack pointer and data area (in DPRAM)
173 */
174 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
175 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
176 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
177 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
179 /*-----------------------------------------------------------------------
180 * Start addresses for the final memory configuration
181 * (Set up by the startup code)
182 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
183 */
184 #define CONFIG_SYS_SDRAM_BASE 0x00000000
185 #define CONFIG_SYS_FLASH_BASE 0x40000000
186 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
188 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
190 /*
191 * For booting Linux, the board info and command line data
192 * have to be in the first 8 MB of memory, since this is
193 * the maximum mapped by the Linux kernel during initialization.
194 */
195 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
197 /*-----------------------------------------------------------------------
198 * FLASH organization
199 */
201 /* use CFI flash driver */
202 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
203 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
204 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
205 #define CONFIG_SYS_FLASH_EMPTY_INFO
206 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
207 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
208 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
210 #define CONFIG_ENV_IS_IN_FLASH 1
211 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
212 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
213 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
215 /* Address and size of Redundant Environment Sector */
216 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
217 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
219 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
221 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
223 /*-----------------------------------------------------------------------
224 * Dynamic MTD partition support
225 */
226 #define CONFIG_CMD_MTDPARTS
227 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
228 #define CONFIG_FLASH_CFI_MTD
229 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
231 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
232 "128k(dtb)," \
233 "1920k(kernel)," \
234 "5632(rootfs)," \
235 "4m(data)"
237 /*-----------------------------------------------------------------------
238 * Hardware Information Block
239 */
240 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
241 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
242 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
244 /*-----------------------------------------------------------------------
245 * Cache Configuration
246 */
247 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
248 #if defined(CONFIG_CMD_KGDB)
249 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
250 #endif
252 /*-----------------------------------------------------------------------
253 * SYPCR - System Protection Control 11-9
254 * SYPCR can only be written once after reset!
255 *-----------------------------------------------------------------------
256 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
257 */
258 #if defined(CONFIG_WATCHDOG)
259 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
260 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
261 #else
262 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
263 #endif
265 /*-----------------------------------------------------------------------
266 * SIUMCR - SIU Module Configuration 11-6
267 *-----------------------------------------------------------------------
268 * PCMCIA config., multi-function pin tri-state
269 */
270 #ifndef CONFIG_CAN_DRIVER
271 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
272 #else /* we must activate GPL5 in the SIUMCR for CAN */
273 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
274 #endif /* CONFIG_CAN_DRIVER */
276 /*-----------------------------------------------------------------------
277 * TBSCR - Time Base Status and Control 11-26
278 *-----------------------------------------------------------------------
279 * Clear Reference Interrupt Status, Timebase freezing enabled
280 */
281 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
283 /*-----------------------------------------------------------------------
284 * RTCSC - Real-Time Clock Status and Control Register 11-27
285 *-----------------------------------------------------------------------
286 */
287 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
289 /*-----------------------------------------------------------------------
290 * PISCR - Periodic Interrupt Status and Control 11-31
291 *-----------------------------------------------------------------------
292 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
293 */
294 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
296 /*-----------------------------------------------------------------------
297 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
298 *-----------------------------------------------------------------------
299 * Reset PLL lock status sticky bit, timer expired status bit and timer
300 * interrupt status bit
301 */
302 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
304 /*-----------------------------------------------------------------------
305 * SCCR - System Clock and reset Control Register 15-27
306 *-----------------------------------------------------------------------
307 * Set clock output, timebase and RTC source and divider,
308 * power management and some other internal clocks
309 */
310 #define SCCR_MASK SCCR_EBDF11
311 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
312 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
313 SCCR_DFALCD00)
315 /*-----------------------------------------------------------------------
316 * PCMCIA stuff
317 *-----------------------------------------------------------------------
318 *
319 */
320 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
321 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
322 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
323 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
324 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
325 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
326 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
327 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
329 /*-----------------------------------------------------------------------
330 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
331 *-----------------------------------------------------------------------
332 */
334 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
335 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
337 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
338 #undef CONFIG_IDE_LED /* LED for ide not supported */
339 #undef CONFIG_IDE_RESET /* reset for ide not supported */
341 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
342 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
344 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
346 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
348 /* Offset for data I/O */
349 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
351 /* Offset for normal register accesses */
352 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
354 /* Offset for alternate registers */
355 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
357 /*-----------------------------------------------------------------------
358 *
359 *-----------------------------------------------------------------------
360 *
361 */
362 #define CONFIG_SYS_DER 0
364 /*
365 * Init Memory Controller:
366 *
367 * BR0/1 and OR0/1 (FLASH)
368 */
370 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
371 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
373 /* used to re-map FLASH both when starting from SRAM or FLASH:
374 * restrict access enough to keep SRAM working (if any)
375 * but not too much to meddle with FLASH accesses
376 */
377 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
378 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
380 /*
381 * FLASH timing:
382 */
383 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
384 OR_SCY_3_CLK | OR_EHTR | OR_BI)
386 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
387 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
388 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
390 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
391 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
392 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
394 /*
395 * BR2/3 and OR2/3 (SDRAM)
396 *
397 */
398 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
399 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
400 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
402 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
403 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
405 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
406 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
408 #ifndef CONFIG_CAN_DRIVER
409 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
410 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
411 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
412 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
413 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
414 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
415 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
416 BR_PS_8 | BR_MS_UPMB | BR_V )
417 #endif /* CONFIG_CAN_DRIVER */
419 /*
420 * Memory Periodic Timer Prescaler
421 *
422 * The Divider for PTA (refresh timer) configuration is based on an
423 * example SDRAM configuration (64 MBit, one bank). The adjustment to
424 * the number of chip selects (NCS) and the actually needed refresh
425 * rate is done by setting MPTPR.
426 *
427 * PTA is calculated from
428 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
429 *
430 * gclk CPU clock (not bus clock!)
431 * Trefresh Refresh cycle * 4 (four word bursts used)
432 *
433 * 4096 Rows from SDRAM example configuration
434 * 1000 factor s -> ms
435 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
436 * 4 Number of refresh cycles per period
437 * 64 Refresh cycle in ms per number of rows
438 * --------------------------------------------
439 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
440 *
441 * 50 MHz => 50.000.000 / Divider = 98
442 * 66 Mhz => 66.000.000 / Divider = 129
443 * 80 Mhz => 80.000.000 / Divider = 156
444 */
446 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
447 #define CONFIG_SYS_MAMR_PTA 98
449 /*
450 * For 16 MBit, refresh rates could be 31.3 us
451 * (= 64 ms / 2K = 125 / quad bursts).
452 * For a simpler initialization, 15.6 us is used instead.
453 *
454 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
455 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
456 */
457 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
458 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
460 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
461 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
462 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
464 /*
465 * MAMR settings for SDRAM
466 */
468 /* 8 column SDRAM */
469 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
470 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
472 /* 9 column SDRAM */
473 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
474 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
477 /* pass open firmware flat tree */
478 #define CONFIG_OF_LIBFDT 1
479 #define CONFIG_OF_BOARD_SETUP 1
480 #define CONFIG_HWCONFIG 1
482 #endif /* __CONFIG_H */