1 /*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 /* ------------------------------------------------------------------------- */
26 /*
27 * board/config.h - configuration options, board specific
28 */
30 #ifndef __CONFIG_H
31 #define __CONFIG_H
33 /*
34 * High Level Configuration Options
35 * (easy to change)
36 */
38 #define CONFIG_MPC824X 1
39 /* #define CONFIG_MPC8240 1 */
40 #define CONFIG_MPC8245 1
41 #define CONFIG_EXALION 1
43 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
45 #if defined (CONFIG_MPC8240)
46 /* #warning ---------- eXalion with MPC8240 --------------- */
47 #elif defined (CONFIG_MPC8245)
48 /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */
49 #elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
50 #error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
51 #else
52 #error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
53 #endif
54 /* older kernels need clock in MHz newer in Hz */
55 /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */
56 #undef CONFIG_CLOCKS_IN_MHZ
58 #define CONFIG_BOOTDELAY 10
61 /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
63 /*
64 * BOOTP options
65 */
66 #define CONFIG_BOOTP_BOOTFILESIZE
67 #define CONFIG_BOOTP_BOOTPATH
68 #define CONFIG_BOOTP_GATEWAY
69 #define CONFIG_BOOTP_HOSTNAME
72 /*
73 * Command line configuration.
74 */
75 #include <config_cmd_default.h>
77 #define CONFIG_CMD_FLASH
78 #define CONFIG_CMD_SDRAM
79 #define CONFIG_CMD_I2C
80 #define CONFIG_CMD_IDE
81 #define CONFIG_CMD_FAT
82 #define CONFIG_CMD_SAVEENV
83 #define CONFIG_CMD_PCI
86 /*-----------------------------------------------------------------------
87 * Miscellaneous configurable options
88 */
89 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
90 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
91 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
92 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
93 #define CONFIG_SYS_MAXARGS 8 /* max number of command args */
94 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
95 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
96 #define CONFIG_MISC_INIT_R 1
98 /*-----------------------------------------------------------------------
99 * Start addresses for the final memory configuration
100 * (Set up by the startup code)
101 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
102 */
103 #define CONFIG_SYS_SDRAM_BASE 0x00000000
104 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */
105 /* return real value. */
107 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
109 #undef CONFIG_SYS_RAMBOOT
110 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
111 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
113 /*-----------------------------------------------------------------------
114 * Definitions for initial stack pointer and data area
115 */
116 #define CONFIG_SYS_INIT_DATA_SIZE 128
118 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
119 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
120 #define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
122 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
123 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
126 #if defined (CONFIG_MPC8240)
127 #define CONFIG_SYS_FLASH_BASE 0xFFE00000
128 #define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */
129 #elif defined (CONFIG_MPC8245)
130 #define CONFIG_SYS_FLASH_BASE 0xFFC00000
131 #define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */
132 #else
133 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
134 #endif
136 #define CONFIG_ENV_IS_IN_FLASH 1
137 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */
138 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */
139 #define CONFIG_ENV_ADDR 0xFFFC0000
140 #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
142 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
144 #define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
145 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
146 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
148 #define CONFIG_SYS_EUMB_ADDR 0xFC000000
150 /* #define CONFIG_SYS_ISA_MEM 0xFD000000 */
151 #define CONFIG_SYS_ISA_IO 0xFE000000
153 /*-----------------------------------------------------------------------
154 * FLASH organization
155 */
156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
157 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
159 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
160 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
162 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE
163 #define FLASH_BASE1_PRELIM 0
166 /*-----------------------------------------------------------------------
167 * FLASH and environment organization
168 */
170 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
171 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
172 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
173 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
174 #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
175 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
176 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
179 /*-----------------------------------------------------------------------
180 * PCI stuff
181 */
182 #define CONFIG_PCI 1 /* include pci support */
183 #undef CONFIG_PCI_PNP
186 #define CONFIG_EEPRO100 1
188 #define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */
189 #define PCI_ENET0_IOADDR 0x80000000
190 #define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */
191 #define PCI_ENET1_IOADDR 0x81000000
192 #define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */
193 #define PCI_ENET2_IOADDR 0x82000000
194 #define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */
195 #define PCI_ENET3_IOADDR 0x83000000
197 /*-----------------------------------------------------------------------
198 * NS16550 Configuration
199 */
200 #define CONFIG_SYS_NS16550 1
201 #define CONFIG_SYS_NS16550_SERIAL 1
203 #define CONFIG_CONS_INDEX 1
204 #define CONFIG_BAUDRATE 38400
206 #define CONFIG_SYS_NS16550_REG_SIZE 1
208 #if (CONFIG_CONS_INDEX == 1)
209 #define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */
210 #else
211 #define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
212 #endif
214 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8)
215 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500)
216 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600)
218 /*-----------------------------------------------------------------------
219 * select i2c support configuration
220 *
221 * Supported configurations are {none, software, hardware} drivers.
222 * If the software driver is chosen, there are some additional
223 * configuration items that the driver uses to drive the port pins.
224 */
225 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
226 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
227 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
228 #define CONFIG_SYS_I2C_SLAVE 0x7F
230 /*-----------------------------------------------------------------------
231 * Low Level Configuration Settings
232 * (address mappings, register initial values, etc.)
233 * You should know what you are doing if you make changes here.
234 */
235 #define CONFIG_SYS_HZ 1000
237 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
238 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
240 /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */
242 #if defined (CONFIG_MPC8245)
243 /* Bit-field values for PMCR2. */
244 #if defined (CONFIG_133MHZ_DRAM)
245 #define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */
246 #define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */
247 #endif
249 /* Bit-field values for MIOCR1. */
250 #if !defined (CONFIG_133MHZ_DRAM)
251 #define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */
252 #endif
253 /* Bit-field values for MIOCR2. */
254 #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */
255 /* - note bottom 3 bits MUST be 0 */
256 #endif
258 /* Bit-field values for MCCR1. */
259 #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
260 #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
262 /* Bit-field values for MCCR2. */
263 #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
264 #if defined (CONFIG_133MHZ_DRAM)
265 #define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */
266 #else /* refresh cycles */
267 #define CONFIG_SYS_REFINT 750
268 #endif
270 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
271 #if defined (CONFIG_133MHZ_DRAM)
272 #define CONFIG_SYS_BSTOPRE 1023
273 #else
274 #define CONFIG_SYS_BSTOPRE 250
275 #endif
277 /* Bit-field values for MCCR3. */
278 /* the following are for SDRAM only */
280 #if defined (CONFIG_133MHZ_DRAM)
281 #define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */
282 #else
283 #define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */
284 #endif
285 #if defined (CONFIG_MPC8240)
286 #define CONFIG_SYS_RDLAT 2 /* data latency from read command */
287 #endif
289 /* Bit-field values for MCCR4. */
290 #if defined (CONFIG_133MHZ_DRAM)
291 #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
292 #define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */
293 #define CONFIG_SYS_ACTORW 5 /* Activate to R/W */
294 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
295 #else
296 #if 0
297 #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
298 #define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
299 #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
300 #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
301 #endif
302 #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
303 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
304 #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
305 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
306 #endif
307 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
308 #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
309 #define CONFIG_SYS_REGDIMM 0
310 #if defined (CONFIG_MPC8240)
311 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0
312 #elif defined (CONFIG_MPC8245)
313 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
314 #define CONFIG_SYS_EXTROM 0
315 #else
316 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
317 #endif
320 /*-----------------------------------------------------------------------
321 memory bank settings
322 * only bits 20-29 are actually used from these vales to set the
323 * start/end address the upper two bits will be 0, and the lower 20
324 * bits will be set to 0x00000 for a start address, or 0xfffff for an
325 * end address
326 */
327 #define CONFIG_SYS_BANK0_START 0x00000000
328 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
329 #define CONFIG_SYS_BANK0_ENABLE 1
330 #define CONFIG_SYS_BANK1_START 0x3ff00000
331 #define CONFIG_SYS_BANK1_END 0x3fffffff
332 #define CONFIG_SYS_BANK1_ENABLE 0
333 #define CONFIG_SYS_BANK2_START 0x3ff00000
334 #define CONFIG_SYS_BANK2_END 0x3fffffff
335 #define CONFIG_SYS_BANK2_ENABLE 0
336 #define CONFIG_SYS_BANK3_START 0x3ff00000
337 #define CONFIG_SYS_BANK3_END 0x3fffffff
338 #define CONFIG_SYS_BANK3_ENABLE 0
339 #define CONFIG_SYS_BANK4_START 0x00000000
340 #define CONFIG_SYS_BANK4_END 0x00000000
341 #define CONFIG_SYS_BANK4_ENABLE 0
342 #define CONFIG_SYS_BANK5_START 0x00000000
343 #define CONFIG_SYS_BANK5_END 0x00000000
344 #define CONFIG_SYS_BANK5_ENABLE 0
345 #define CONFIG_SYS_BANK6_START 0x00000000
346 #define CONFIG_SYS_BANK6_END 0x00000000
347 #define CONFIG_SYS_BANK6_ENABLE 0
348 #define CONFIG_SYS_BANK7_START 0x00000000
349 #define CONFIG_SYS_BANK7_END 0x00000000
350 #define CONFIG_SYS_BANK7_ENABLE 0
352 /*-----------------------------------------------------------------------
353 * Memory bank enable bitmask, specifying which of the banks defined above
354 are actually present. MSB is for bank #7, LSB is for bank #0.
355 */
356 #define CONFIG_SYS_BANK_ENABLE 0x01
358 #if defined (CONFIG_MPC8240)
359 #define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */
360 /* see 8240 book for bit definitions */
361 #elif defined (CONFIG_MPC8245)
362 #if defined (CONFIG_133MHZ_DRAM)
363 #define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */
364 #else
365 #define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */
366 #endif
367 #else
368 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
369 #endif
371 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
372 /* currently accessed page in memory */
373 /* see 8240 book for details */
375 /*-----------------------------------------------------------------------
376 * Block Address Translation (BAT) register settings.
377 */
378 /* SDRAM 0 - 256MB */
379 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
380 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
382 /* stack in DCACHE @ 1GB (no backing mem) */
383 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
384 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
386 /* PCI memory */
387 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
388 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
390 /* Flash, config addrs, etc */
391 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
392 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
394 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
395 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
396 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
397 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
398 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
399 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
400 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
401 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
404 /*-----------------------------------------------------------------------
405 * Cache Configuration
406 */
407 #define CONFIG_SYS_CACHELINE_SIZE 32
408 #if defined(CONFIG_CMD_KGDB)
409 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
410 #endif
412 /* values according to the manual */
413 #define CONFIG_DRAM_50MHZ 1
414 #define CONFIG_SDRAM_50MHZ
416 #undef NR_8259_INTS
417 #define NR_8259_INTS 1
419 /*-----------------------------------------------------------------------
420 * IDE/ATA stuff
421 */
422 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
423 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */
425 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */
426 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
427 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
428 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
429 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
430 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
432 #define CONFIG_ATAPI
434 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
435 #undef CONFIG_IDE_LED /* no led for ide supported */
436 #undef CONFIG_IDE_RESET /* reset for ide supported... */
437 #undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
439 /*-----------------------------------------------------------------------
440 * DISK Partition support
441 */
442 #define CONFIG_DOS_PARTITION
444 /*-----------------------------------------------------------------------
445 * For booting Linux, the board info and command line data
446 * have to be in the first 8 MB of memory, since this is
447 * the maximum mapped by the Linux kernel during initialization.
448 */
449 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
451 #endif /* __CONFIG_H */