1 /*
2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
24 /*
25 * board/config.h - configuration options, board specific
26 */
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
31 /* External logbuffer support */
32 #define CONFIG_LOGBUFFER
34 /*
35 * High Level Configuration Options
36 * (easy to change)
37 */
39 #define CONFIG_MPC823 1 /* This is a MPC823E CPU */
40 #define CONFIG_LWMON 1 /* ...on a LWMON board */
42 #define CONFIG_SYS_TEXT_BASE 0x40000000
44 /* Default Ethernet MAC address */
45 #define CONFIG_ETHADDR 00:11:B0:00:00:00
47 /* The default Ethernet MAC address can be overwritten just once */
48 #ifdef CONFIG_ETHADDR
49 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
50 #endif
52 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
53 #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */
54 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
56 #define CONFIG_LCD 1 /* use LCD controller ... */
57 #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
59 #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
60 #define CONFIG_LCD_INFO 1 /* ... and some board info */
61 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
63 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
64 #define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
66 #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
68 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
70 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
72 /* pre-boot commands */
73 #define CONFIG_PREBOOT "setenv bootdelay 15"
75 #undef CONFIG_BOOTARGS
77 /* POST support */
78 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
79 CONFIG_SYS_POST_WATCHDOG | \
80 CONFIG_SYS_POST_RTC | \
81 CONFIG_SYS_POST_MEMORY | \
82 CONFIG_SYS_POST_CPU | \
83 CONFIG_SYS_POST_UART | \
84 CONFIG_SYS_POST_ETHER | \
85 CONFIG_SYS_POST_I2C | \
86 CONFIG_SYS_POST_SPI | \
87 CONFIG_SYS_POST_USB | \
88 CONFIG_SYS_POST_SPR | \
89 CONFIG_SYS_POST_SYSMON)
91 /*
92 * Keyboard commands:
93 * # = 0x28 = ENTER : enable bootmessages on LCD
94 * 2 = 0x3A+0x3C = F1 + F3 : enable update mode
95 * 3 = 0x3C+0x3F = F3 + F6 : enable test mode
96 */
98 #define CONFIG_BOOTCOMMAND "source 40040000;saveenv"
100 /* "gatewayip=10.8.211.250\0" \ */
101 #define CONFIG_EXTRA_ENV_SETTINGS \
102 "kernel_addr=40080000\0" \
103 "ramdisk_addr=40280000\0" \
104 "netmask=255.255.192.0\0" \
105 "serverip=10.8.2.101\0" \
106 "ipaddr=10.8.57.0\0" \
107 "magic_keys=#23\0" \
108 "key_magic#=28\0" \
109 "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
110 "key_magic2=3A+3C\0" \
111 "key_cmd2=echo *** Entering Update Mode ***;" \
112 "if fatload ide 0:3 10000 update.scr;" \
113 "then source 10000;" \
114 "else echo *** UPDATE FAILED ***;" \
115 "fi\0" \
116 "key_magic3=3C+3F\0" \
117 "key_cmd3=echo *** Entering Test Mode ***;" \
118 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
119 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
120 "ramargs=setenv bootargs root=/dev/ram rw\0" \
121 "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
122 "addip=setenv bootargs $bootargs " \
123 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
124 "panic=1\0" \
125 "add_wdt=setenv bootargs $bootargs $wdt_args\0" \
126 "add_misc=setenv bootargs $bootargs runmode\0" \
127 "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
128 "bootm $kernel_addr\0" \
129 "flash_self=run ramargs addip add_wdt addfb add_misc;" \
130 "bootm $kernel_addr $ramdisk_addr\0" \
131 "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
132 "run nfsargs addip add_wdt addfb;bootm\0" \
133 "rootpath=/opt/eldk/ppc_8xx\0" \
134 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
135 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
136 "wdt_args=wdt_8xx=off\0" \
137 "verify=no"
139 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
140 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
142 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
143 #define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 20)
145 #undef CONFIG_STATUS_LED /* Status LED disabled */
147 /* enable I2C and select the hardware/software driver */
148 #undef CONFIG_HARD_I2C /* I2C with hardware support */
149 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
151 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
152 #define CONFIG_SYS_I2C_SLAVE 0xFE
154 #ifdef CONFIG_SOFT_I2C
155 /*
156 * Software (bit-bang) I2C driver configuration
157 */
158 #define PB_SCL 0x00000020 /* PB 26 */
159 #define PB_SDA 0x00000010 /* PB 27 */
161 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
162 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
163 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
164 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
165 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
166 else immr->im_cpm.cp_pbdat &= ~PB_SDA
167 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
168 else immr->im_cpm.cp_pbdat &= ~PB_SCL
169 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
170 #endif /* CONFIG_SOFT_I2C */
173 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
176 /*
177 * Command line configuration.
178 */
179 #include <config_cmd_default.h>
181 #define CONFIG_CMD_ASKENV
182 #define CONFIG_CMD_BMP
183 #define CONFIG_CMD_BSP
184 #define CONFIG_CMD_DATE
185 #define CONFIG_CMD_DHCP
186 #define CONFIG_CMD_EEPROM
187 #define CONFIG_CMD_FAT
188 #define CONFIG_CMD_I2C
189 #define CONFIG_CMD_IDE
190 #define CONFIG_CMD_NFS
191 #define CONFIG_CMD_SNTP
193 #ifdef CONFIG_POST
194 #define CONFIG_CMD_DIAG
195 #endif
198 #define CONFIG_MAC_PARTITION
199 #define CONFIG_DOS_PARTITION
201 /*
202 * BOOTP options
203 */
204 #define CONFIG_BOOTP_SUBNETMASK
205 #define CONFIG_BOOTP_GATEWAY
206 #define CONFIG_BOOTP_HOSTNAME
207 #define CONFIG_BOOTP_BOOTPATH
208 #define CONFIG_BOOTP_BOOTFILESIZE
211 /*
212 * Miscellaneous configurable options
213 */
214 #define CONFIG_SYS_LONGHELP /* undef to save memory */
215 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
217 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
219 #if defined(CONFIG_CMD_KGDB)
220 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
221 #else
222 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
223 #endif
224 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
225 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
226 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
228 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
229 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
231 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
233 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
235 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
237 /*
238 * When the watchdog is enabled, output must be fast enough in Linux.
239 */
240 #ifdef CONFIG_WATCHDOG
241 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 57600, 115200 }
242 #endif
244 /*----------------------------------------------------------------------*/
245 #define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
246 #undef CONFIG_MODEM_SUPPORT_DEBUG
248 #define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */
249 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
250 #if 0
251 #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
252 #define CONFIG_AUTOBOOT_PROMPT \
253 "\nEnter password - autoboot in %d sec...\n", bootdelay
254 #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
255 #endif
256 /*----------------------------------------------------------------------*/
258 /*
259 * Low Level Configuration Settings
260 * (address mappings, register initial values, etc.)
261 * You should know what you are doing if you make changes here.
262 */
263 /*-----------------------------------------------------------------------
264 * Internal Memory Mapped Register
265 */
266 #define CONFIG_SYS_IMMR 0xFFF00000
268 /*-----------------------------------------------------------------------
269 * Definitions for initial stack pointer and data area (in DPRAM)
270 */
271 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
272 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
273 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
274 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
276 /*-----------------------------------------------------------------------
277 * Start addresses for the final memory configuration
278 * (Set up by the startup code)
279 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
280 */
281 #define CONFIG_SYS_SDRAM_BASE 0x00000000
282 #define CONFIG_SYS_FLASH_BASE 0x40000000
283 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
284 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
285 #else
286 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
287 #endif
288 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
289 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
291 /*
292 * For booting Linux, the board info and command line data
293 * have to be in the first 8 MB of memory, since this is
294 * the maximum mapped by the Linux kernel during initialization.
295 */
296 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
297 /*-----------------------------------------------------------------------
298 * FLASH organization
299 */
300 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
301 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
303 #define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
304 #define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
305 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
306 #define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */
307 /* Buffer size.
308 We have two flash devices connected in parallel.
309 Each device incorporates a Write Buffer of 32 bytes.
310 */
311 #define CONFIG_SYS_FLASH_BUFFER_SIZE (2*32)
313 /* Put environment in flash which is much faster to boot than using the EEPROM */
314 #define CONFIG_ENV_IS_IN_FLASH 1
315 #define CONFIG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
316 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
317 #define CONFIG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
319 /*-----------------------------------------------------------------------
320 * I2C/EEPROM Configuration
321 */
323 #define CONFIG_SYS_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
324 #define CONFIG_SYS_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
325 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
326 #define CONFIG_SYS_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
327 #define CONFIG_SYS_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
328 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
329 #define CONFIG_SYS_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
331 #undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
333 #ifdef CONFIG_USE_FRAM /* use FRAM */
334 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
335 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
336 #else /* use EEPROM */
337 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
338 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
340 #endif /* CONFIG_USE_FRAM */
341 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
343 /* List of I2C addresses to be verified by POST */
344 #ifdef CONFIG_USE_FRAM
345 #define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
346 CONFIG_SYS_I2C_SYSMON_ADDR, \
347 CONFIG_SYS_I2C_RTC_ADDR, \
348 CONFIG_SYS_I2C_POWER_A_ADDR, \
349 CONFIG_SYS_I2C_POWER_B_ADDR, \
350 CONFIG_SYS_I2C_KEYBD_ADDR, \
351 CONFIG_SYS_I2C_PICIO_ADDR, \
352 CONFIG_SYS_I2C_EEPROM_ADDR, \
353 }
354 #else /* Use EEPROM - which show up on 8 consequtive addresses */
355 #define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
356 CONFIG_SYS_I2C_SYSMON_ADDR, \
357 CONFIG_SYS_I2C_RTC_ADDR, \
358 CONFIG_SYS_I2C_POWER_A_ADDR, \
359 CONFIG_SYS_I2C_POWER_B_ADDR, \
360 CONFIG_SYS_I2C_KEYBD_ADDR, \
361 CONFIG_SYS_I2C_PICIO_ADDR, \
362 CONFIG_SYS_I2C_EEPROM_ADDR+0, \
363 CONFIG_SYS_I2C_EEPROM_ADDR+1, \
364 CONFIG_SYS_I2C_EEPROM_ADDR+2, \
365 CONFIG_SYS_I2C_EEPROM_ADDR+3, \
366 CONFIG_SYS_I2C_EEPROM_ADDR+4, \
367 CONFIG_SYS_I2C_EEPROM_ADDR+5, \
368 CONFIG_SYS_I2C_EEPROM_ADDR+6, \
369 CONFIG_SYS_I2C_EEPROM_ADDR+7, \
370 }
371 #endif /* CONFIG_USE_FRAM */
373 /*-----------------------------------------------------------------------
374 * Cache Configuration
375 */
376 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
377 #if defined(CONFIG_CMD_KGDB)
378 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
379 #endif
381 /*-----------------------------------------------------------------------
382 * SYPCR - System Protection Control 11-9
383 * SYPCR can only be written once after reset!
384 *-----------------------------------------------------------------------
385 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
386 */
387 #if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
388 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
389 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
390 #else
391 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
392 #endif
394 /*-----------------------------------------------------------------------
395 * SIUMCR - SIU Module Configuration 11-6
396 *-----------------------------------------------------------------------
397 * PCMCIA config., multi-function pin tri-state
398 */
399 /* EARB, DBGC and DBPC are initialised by the HCW */
400 /* => 0x000000C0 */
401 #define CONFIG_SYS_SIUMCR (SIUMCR_GB5E)
402 /*#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
404 /*-----------------------------------------------------------------------
405 * TBSCR - Time Base Status and Control 11-26
406 *-----------------------------------------------------------------------
407 * Clear Reference Interrupt Status, Timebase freezing enabled
408 */
409 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
411 /*-----------------------------------------------------------------------
412 * PISCR - Periodic Interrupt Status and Control 11-31
413 *-----------------------------------------------------------------------
414 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
415 */
416 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
418 /*-----------------------------------------------------------------------
419 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
420 *-----------------------------------------------------------------------
421 * Reset PLL lock status sticky bit, timer expired status bit and timer
422 * interrupt status bit, set PLL multiplication factor !
423 */
424 /* 0x00405000 */
425 #define CONFIG_SYS_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
426 #define CONFIG_SYS_PLPRCR \
427 ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
428 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
429 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
430 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
431 )
433 #define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*13200000)
435 /*-----------------------------------------------------------------------
436 * SCCR - System Clock and reset Control Register 15-27
437 *-----------------------------------------------------------------------
438 * Set clock output, timebase and RTC source and divider,
439 * power management and some other internal clocks
440 */
441 #define SCCR_MASK SCCR_EBDF11
442 /* 0x01800000 */
443 #define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
444 SCCR_RTDIV | SCCR_RTSEL | \
445 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
446 SCCR_EBDF00 | SCCR_DFSYNC00 | \
447 SCCR_DFBRG00 | SCCR_DFNL000 | \
448 SCCR_DFNH000 | SCCR_DFLCD100 | \
449 SCCR_DFALCD01)
451 /*-----------------------------------------------------------------------
452 * RTCSC - Real-Time Clock Status and Control Register 11-27
453 *-----------------------------------------------------------------------
454 */
455 /* 0x00C3 => 0x0003 */
456 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
459 /*-----------------------------------------------------------------------
460 * RCCR - RISC Controller Configuration Register 19-4
461 *-----------------------------------------------------------------------
462 */
463 #define CONFIG_SYS_RCCR 0x0000
465 /*-----------------------------------------------------------------------
466 * RMDS - RISC Microcode Development Support Control Register
467 *-----------------------------------------------------------------------
468 */
469 #define CONFIG_SYS_RMDS 0
471 /*-----------------------------------------------------------------------
472 *
473 * Interrupt Levels
474 *-----------------------------------------------------------------------
475 */
476 #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
478 /*-----------------------------------------------------------------------
479 * PCMCIA stuff
480 *-----------------------------------------------------------------------
481 *
482 */
483 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000)
484 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
485 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000)
486 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
487 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000)
488 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
489 #define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000)
490 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
492 /*-----------------------------------------------------------------------
493 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
494 *-----------------------------------------------------------------------
495 */
497 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
498 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
500 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
501 #undef CONFIG_IDE_LED /* LED for ide not supported */
502 #undef CONFIG_IDE_RESET /* reset for ide not supported */
504 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
505 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
507 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
509 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
511 /* Offset for data I/O */
512 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
514 /* Offset for normal register accesses */
515 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
517 /* Offset for alternate registers */
518 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
520 #define CONFIG_SUPPORT_VFAT /* enable VFAT support */
522 /*-----------------------------------------------------------------------
523 *
524 *-----------------------------------------------------------------------
525 *
526 */
527 #define CONFIG_SYS_DER 0
529 /*
530 * Init Memory Controller:
531 *
532 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
533 */
535 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
536 #define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
538 /* used to re-map FLASH:
539 * restrict access enough to keep SRAM working (if any)
540 * but not too much to meddle with FLASH accesses
541 */
542 #define CONFIG_SYS_REMAP_OR_AM 0xFF000000 /* OR addr mask */
543 #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
545 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
546 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK)
548 #define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
549 CONFIG_SYS_OR_TIMING_FLASH)
550 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
551 CONFIG_SYS_OR_TIMING_FLASH)
552 /* 16 bit, bank valid */
553 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
555 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
556 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
557 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
559 /*
560 * BR3/OR3: SDRAM
561 *
562 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
563 */
564 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
565 #define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
566 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
568 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
570 #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
571 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
573 /*
574 * BR5/OR5: Touch Panel
575 *
576 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
577 */
578 #define TOUCHPNL_BASE 0x20000000
579 #define TOUCHPNL_OR_AM 0xFFFF8000
580 #define TOUCHPNL_TIMING OR_SCY_0_CLK
582 #define CONFIG_SYS_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
583 TOUCHPNL_TIMING )
584 #define CONFIG_SYS_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
586 #define CONFIG_SYS_MEMORY_75
587 #undef CONFIG_SYS_MEMORY_7E
588 #undef CONFIG_SYS_MEMORY_8E
590 /*
591 * Memory Periodic Timer Prescaler
592 */
594 /* periodic timer for refresh */
595 #define CONFIG_SYS_MPTPR 0x200
597 /*
598 * MAMR settings for SDRAM
599 */
601 #define CONFIG_SYS_MAMR_8COL 0x80802114
602 #define CONFIG_SYS_MAMR_9COL 0x80904114
604 /*
605 * MAR setting for SDRAM
606 */
607 #define CONFIG_SYS_MAR 0x00000088
609 #endif /* __CONFIG_H */