1 /*
2 * linux/include/linux/mtd/nand.h
3 *
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Info:
13 * Contains standard defines and IDs for NAND flash devices
14 *
15 * Changelog:
16 * See git changelog.
17 */
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include "config.h"
23 #include "linux/compat.h"
24 #include "linux/mtd/mtd.h"
25 #include "linux/mtd/bbm.h"
28 struct mtd_info;
29 struct nand_flash_dev;
30 /* Scan and identify a NAND device */
31 extern int nand_scan (struct mtd_info *mtd, int max_chips);
32 /* Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type */
34 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
35 const struct nand_flash_dev *table);
36 extern int nand_scan_tail(struct mtd_info *mtd);
38 /* Free resources held by the NAND device */
39 extern void nand_release(struct mtd_info *mtd);
41 /* Internal helper for board drivers which need to override command function */
42 extern void nand_wait_ready(struct mtd_info *mtd);
44 /*
45 * This constant declares the max. oobsize / page, which
46 * is supported now. If you add a chip with bigger oobsize/page
47 * adjust this accordingly.
48 */
49 #define NAND_MAX_OOBSIZE 576
50 #define NAND_MAX_PAGESIZE 8192
52 /*
53 * Constants for hardware specific CLE/ALE/NCE function
54 *
55 * These are bits which can be or'ed to set/clear multiple
56 * bits in one go.
57 */
58 /* Select the chip by setting nCE to low */
59 #define NAND_NCE 0x01
60 /* Select the command latch by setting CLE to high */
61 #define NAND_CLE 0x02
62 /* Select the address latch by setting ALE to high */
63 #define NAND_ALE 0x04
65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
67 #define NAND_CTRL_CHANGE 0x80
69 /*
70 * Standard NAND flash commands
71 */
72 #define NAND_CMD_READ0 0
73 #define NAND_CMD_READ1 1
74 #define NAND_CMD_RNDOUT 5
75 #define NAND_CMD_PAGEPROG 0x10
76 #define NAND_CMD_READOOB 0x50
77 #define NAND_CMD_ERASE1 0x60
78 #define NAND_CMD_STATUS 0x70
79 #define NAND_CMD_STATUS_MULTI 0x71
80 #define NAND_CMD_SEQIN 0x80
81 #define NAND_CMD_RNDIN 0x85
82 #define NAND_CMD_READID 0x90
83 #define NAND_CMD_ERASE2 0xd0
84 #define NAND_CMD_PARAM 0xec
85 #define NAND_CMD_RESET 0xff
87 #define NAND_CMD_LOCK 0x2a
88 #define NAND_CMD_LOCK_TIGHT 0x2c
89 #define NAND_CMD_UNLOCK1 0x23
90 #define NAND_CMD_UNLOCK2 0x24
91 #define NAND_CMD_LOCK_STATUS 0x7a
93 /* Extended commands for large page devices */
94 #define NAND_CMD_READSTART 0x30
95 #define NAND_CMD_RNDOUTSTART 0xE0
96 #define NAND_CMD_CACHEDPROG 0x15
98 /* Extended commands for AG-AND device */
99 /*
100 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
101 * there is no way to distinguish that from NAND_CMD_READ0
102 * until the remaining sequence of commands has been completed
103 * so add a high order bit and mask it off in the command.
104 */
105 #define NAND_CMD_DEPLETE1 0x100
106 #define NAND_CMD_DEPLETE2 0x38
107 #define NAND_CMD_STATUS_MULTI 0x71
108 #define NAND_CMD_STATUS_ERROR 0x72
109 /* multi-bank error status (banks 0-3) */
110 #define NAND_CMD_STATUS_ERROR0 0x73
111 #define NAND_CMD_STATUS_ERROR1 0x74
112 #define NAND_CMD_STATUS_ERROR2 0x75
113 #define NAND_CMD_STATUS_ERROR3 0x76
114 #define NAND_CMD_STATUS_RESET 0x7f
115 #define NAND_CMD_STATUS_CLEAR 0xff
117 #define NAND_CMD_NONE -1
119 /* Status bits */
120 #define NAND_STATUS_FAIL 0x01
121 #define NAND_STATUS_FAIL_N1 0x02
122 #define NAND_STATUS_TRUE_READY 0x20
123 #define NAND_STATUS_READY 0x40
124 #define NAND_STATUS_WP 0x80
126 /*
127 * Constants for ECC_MODES
128 */
129 typedef enum {
130 NAND_ECC_NONE,
131 NAND_ECC_SOFT,
132 NAND_ECC_HW,
133 NAND_ECC_HW_SYNDROME,
134 NAND_ECC_HW_OOB_FIRST,
135 NAND_ECC_SOFT_BCH,
136 } nand_ecc_modes_t;
138 /*
139 * Constants for Hardware ECC
140 */
141 /* Reset Hardware ECC for read */
142 #define NAND_ECC_READ 0
143 /* Reset Hardware ECC for write */
144 #define NAND_ECC_WRITE 1
145 /* Enable Hardware ECC before syndrom is read back from flash */
146 #define NAND_ECC_READSYN 2
148 /* Bit mask for flags passed to do_nand_read_ecc */
149 #define NAND_GET_DEVICE 0x80
152 /*
153 * Option constants for bizarre disfunctionality and real
154 * features.
155 */
156 /* Chip can not auto increment pages */
157 #define NAND_NO_AUTOINCR 0x00000001
158 /* Buswitdh is 16 bit */
159 #define NAND_BUSWIDTH_16 0x00000002
160 /* Device supports partial programming without padding */
161 #define NAND_NO_PADDING 0x00000004
162 /* Chip has cache program function */
163 #define NAND_CACHEPRG 0x00000008
164 /* Chip has copy back function */
165 #define NAND_COPYBACK 0x00000010
166 /*
167 * AND Chip which has 4 banks and a confusing page / block
168 * assignment. See Renesas datasheet for further information.
169 */
170 #define NAND_IS_AND 0x00000020
171 /*
172 * Chip has a array of 4 pages which can be read without
173 * additional ready /busy waits.
174 */
175 #define NAND_4PAGE_ARRAY 0x00000040
176 /*
177 * Chip requires that BBT is periodically rewritten to prevent
178 * bits from adjacent blocks from 'leaking' in altering data.
179 * This happens with the Renesas AG-AND chips, possibly others.
180 */
181 #define BBT_AUTO_REFRESH 0x00000080
182 /*
183 * Chip does not require ready check on read. true
184 * for all large page devices, as they do not support
185 * autoincrement.
186 */
187 #define NAND_NO_READRDY 0x00000100
188 /* Chip does not allow subpage writes */
189 #define NAND_NO_SUBPAGE_WRITE 0x00000200
191 /* Device is one of 'new' xD cards that expose fake nand command set */
192 #define NAND_BROKEN_XD 0x00000400
194 /* Device behaves just like nand, but is readonly */
195 #define NAND_ROM 0x00000800
197 /* Device supports subpage reads */
198 #define NAND_SUBPAGE_READ 0x00001000
200 /* Options valid for Samsung large page devices */
201 #define NAND_SAMSUNG_LP_OPTIONS \
202 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
204 /* Macros to identify the above */
205 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
206 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
207 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
208 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
209 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
211 /* Non chip related options */
212 /*
213 * Use a flash based bad block table. OOB identifier is saved in OOB area.
214 * This option is passed to the default bad block table function.
215 */
216 #define NAND_USE_FLASH_BBT 0x00010000
217 /* This option skips the bbt scan during initialization. */
218 #define NAND_SKIP_BBTSCAN 0x00020000
219 /*
220 * This option is defined if the board driver allocates its own buffers
221 * (e.g. because it needs them DMA-coherent).
222 */
223 #define NAND_OWN_BUFFERS 0x00040000
224 /* Chip may not exist, so silence any errors in scan */
225 #define NAND_SCAN_SILENT_NODEV 0x00080000
226 /*
227 * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
228 * the OOB area.
229 */
230 #define NAND_USE_FLASH_BBT_NO_OOB 0x00800000
231 /* Create an empty BBT with no vendor information if the BBT is available */
232 #define NAND_CREATE_EMPTY_BBT 0x01000000
234 /* Options set by nand scan */
235 /* bbt has already been read */
236 #define NAND_BBT_SCANNED 0x40000000
237 /* Nand scan has allocated controller struct */
238 #define NAND_CONTROLLER_ALLOC 0x80000000
240 /* Cell info constants */
241 #define NAND_CI_CHIPNR_MSK 0x03
242 #define NAND_CI_CELLTYPE_MSK 0x0C
244 /* Keep gcc happy */
245 struct nand_chip;
247 struct nand_onfi_params {
248 /* rev info and features block */
249 /* 'O' 'N' 'F' 'I' */
250 u8 sig[4];
251 __le16 revision;
252 __le16 features;
253 __le16 opt_cmd;
254 u8 reserved[22];
256 /* manufacturer information block */
257 char manufacturer[12];
258 char model[20];
259 u8 jedec_id;
260 __le16 date_code;
261 u8 reserved2[13];
263 /* memory organization block */
264 __le32 byte_per_page;
265 __le16 spare_bytes_per_page;
266 __le32 data_bytes_per_ppage;
267 __le16 spare_bytes_per_ppage;
268 __le32 pages_per_block;
269 __le32 blocks_per_lun;
270 u8 lun_count;
271 u8 addr_cycles;
272 u8 bits_per_cell;
273 __le16 bb_per_lun;
274 __le16 block_endurance;
275 u8 guaranteed_good_blocks;
276 __le16 guaranteed_block_endurance;
277 u8 programs_per_page;
278 u8 ppage_attr;
279 u8 ecc_bits;
280 u8 interleaved_bits;
281 u8 interleaved_ops;
282 u8 reserved3[13];
284 /* electrical parameter block */
285 u8 io_pin_capacitance_max;
286 __le16 async_timing_mode;
287 __le16 program_cache_timing_mode;
288 __le16 t_prog;
289 __le16 t_bers;
290 __le16 t_r;
291 __le16 t_ccs;
292 __le16 src_sync_timing_mode;
293 __le16 src_ssync_features;
294 __le16 clk_pin_capacitance_typ;
295 __le16 io_pin_capacitance_typ;
296 __le16 input_pin_capacitance_typ;
297 u8 input_pin_capacitance_max;
298 u8 driver_strenght_support;
299 __le16 t_int_r;
300 __le16 t_ald;
301 u8 reserved4[7];
303 /* vendor */
304 u8 reserved5[90];
306 __le16 crc;
307 } __attribute__((packed));
309 #define ONFI_CRC_BASE 0x4F4E
311 /**
312 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
313 * @lock: protection lock
314 * @active: the mtd device which holds the controller currently
315 * @wq: wait queue to sleep on if a NAND operation is in
316 * progress used instead of the per chip wait queue
317 * when a hw controller is available.
318 */
319 struct nand_hw_control {
320 /* XXX U-BOOT XXX */
321 #if 0
322 spinlock_t lock;
323 wait_queue_head_t wq;
324 #endif
325 struct nand_chip *active;
326 };
328 /**
329 * struct nand_ecc_ctrl - Control structure for ecc
330 * @mode: ecc mode
331 * @steps: number of ecc steps per page
332 * @size: data bytes per ecc step
333 * @bytes: ecc bytes per step
334 * @total: total number of ecc bytes per page
335 * @prepad: padding information for syndrome based ecc generators
336 * @postpad: padding information for syndrome based ecc generators
337 * @layout: ECC layout control struct pointer
338 * @priv: pointer to private ecc control data
339 * @hwctl: function to control hardware ecc generator. Must only
340 * be provided if an hardware ECC is available
341 * @calculate: function for ecc calculation or readback from ecc hardware
342 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
343 * @read_page_raw: function to read a raw page without ECC
344 * @write_page_raw: function to write a raw page without ECC
345 * @read_page: function to read a page according to the ecc generator
346 * requirements.
347 * @read_subpage: function to read parts of the page covered by ECC.
348 * @write_page: function to write a page according to the ecc generator
349 * requirements.
350 * @read_oob: function to read chip OOB data
351 * @write_oob: function to write chip OOB data
352 */
353 struct nand_ecc_ctrl {
354 nand_ecc_modes_t mode;
355 int steps;
356 int size;
357 int bytes;
358 int total;
359 int prepad;
360 int postpad;
361 struct nand_ecclayout *layout;
362 void *priv;
363 void (*hwctl)(struct mtd_info *mtd, int mode);
364 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
365 uint8_t *ecc_code);
366 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
367 uint8_t *calc_ecc);
368 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
369 uint8_t *buf, int page);
370 void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
371 const uint8_t *buf);
372 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
373 uint8_t *buf, int page);
374 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
375 uint32_t offs, uint32_t len, uint8_t *buf);
376 void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
377 const uint8_t *buf);
378 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
379 int sndcmd);
380 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
381 int page);
382 };
384 /**
385 * struct nand_buffers - buffer structure for read/write
386 * @ecccalc: buffer for calculated ecc
387 * @ecccode: buffer for ecc read from flash
388 * @databuf: buffer for data - dynamically sized
389 *
390 * Do not change the order of buffers. databuf and oobrbuf must be in
391 * consecutive order.
392 */
393 struct nand_buffers {
394 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
395 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
396 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
397 ARCH_DMA_MINALIGN)];
398 };
400 /**
401 * struct nand_chip - NAND Private Flash Chip Data
402 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
403 * flash device
404 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
405 * flash device.
406 * @read_byte: [REPLACEABLE] read one byte from the chip
407 * @read_word: [REPLACEABLE] read one word from the chip
408 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
409 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
410 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip
411 * data.
412 * @select_chip: [REPLACEABLE] select chip nr
413 * @block_bad: [REPLACEABLE] check, if the block is bad
414 * @block_markbad: [REPLACEABLE] mark the block bad
415 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
416 * ALE/CLE/nCE. Also used to write command and address
417 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
418 * mtd->oobsize, mtd->writesize and so on.
419 * @id_data contains the 8 bytes values of NAND_CMD_READID.
420 * Return with the bus width.
421 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing
422 * device ready/busy line. If set to NULL no access to
423 * ready/busy is available and the ready/busy information
424 * is read from the chip status register.
425 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
426 * commands to the chip.
427 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
428 * ready.
429 * @ecc: [BOARDSPECIFIC] ecc control ctructure
430 * @buffers: buffer structure for read/write
431 * @hwcontrol: platform-specific hardware control structure
432 * @ops: oob operation operands
433 * @erase_cmd: [INTERN] erase command write function, selectable due
434 * to AND support.
435 * @scan_bbt: [REPLACEABLE] function to scan bad block table
436 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
437 * data from array to read regs (tR).
438 * @state: [INTERN] the current state of the NAND device
439 * @oob_poi: poison value buffer
440 * @page_shift: [INTERN] number of address bits in a page (column
441 * address bits).
442 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
443 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
444 * @chip_shift: [INTERN] number of address bits in one chip
445 * @options: [BOARDSPECIFIC] various chip options. They can partly
446 * be set to inform nand_scan about special functionality.
447 * See the defines for further explanation.
448 * @badblockpos: [INTERN] position of the bad block marker in the oob
449 * area.
450 * @badblockbits: [INTERN] number of bits to left-shift the bad block
451 * number
452 * @cellinfo: [INTERN] MLC/multichip data from chip ident
453 * @numchips: [INTERN] number of physical chips
454 * @chipsize: [INTERN] the size of one chip for multichip arrays
455 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
456 * @pagebuf: [INTERN] holds the pagenumber which is currently in
457 * data_buf.
458 * @subpagesize: [INTERN] holds the subpagesize
459 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
460 * non 0 if ONFI supported.
461 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
462 * supported, 0 otherwise.
463 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
464 * @bbt: [INTERN] bad block table pointer
465 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
466 * lookup.
467 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
468 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
469 * bad block scan.
470 * @controller: [REPLACEABLE] a pointer to a hardware controller
471 * structure which is shared among multiple independend
472 * devices.
473 * @priv: [OPTIONAL] pointer to private chip date
474 * @errstat: [OPTIONAL] hardware specific function to perform
475 * additional error status checks (determine if errors are
476 * correctable).
477 * @write_page: [REPLACEABLE] High-level page write function
478 */
480 struct nand_chip {
481 void __iomem *IO_ADDR_R;
482 void __iomem *IO_ADDR_W;
484 uint8_t (*read_byte)(struct mtd_info *mtd);
485 u16 (*read_word)(struct mtd_info *mtd);
486 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
487 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
488 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
489 void (*select_chip)(struct mtd_info *mtd, int chip);
490 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
491 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
492 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
493 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
494 u8 *id_data);
495 int (*dev_ready)(struct mtd_info *mtd);
496 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
497 int page_addr);
498 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
499 void (*erase_cmd)(struct mtd_info *mtd, int page);
500 int (*scan_bbt)(struct mtd_info *mtd);
501 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
502 int status, int page);
503 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
504 const uint8_t *buf, int page, int cached, int raw);
506 int chip_delay;
507 unsigned int options;
509 int page_shift;
510 int phys_erase_shift;
511 int bbt_erase_shift;
512 int chip_shift;
513 int numchips;
514 uint64_t chipsize;
515 int pagemask;
516 int pagebuf;
517 int subpagesize;
518 uint8_t cellinfo;
519 int badblockpos;
520 int badblockbits;
522 int onfi_version;
523 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
524 struct nand_onfi_params onfi_params;
525 #endif
527 int state;
529 uint8_t *oob_poi;
530 struct nand_hw_control *controller;
531 struct nand_ecclayout *ecclayout;
533 struct nand_ecc_ctrl ecc;
534 struct nand_buffers *buffers;
535 struct nand_hw_control hwcontrol;
537 struct mtd_oob_ops ops;
539 uint8_t *bbt;
540 struct nand_bbt_descr *bbt_td;
541 struct nand_bbt_descr *bbt_md;
543 struct nand_bbt_descr *badblock_pattern;
545 void *priv;
546 };
548 /*
549 * NAND Flash Manufacturer ID Codes
550 */
551 #define NAND_MFR_TOSHIBA 0x98
552 #define NAND_MFR_SAMSUNG 0xec
553 #define NAND_MFR_FUJITSU 0x04
554 #define NAND_MFR_NATIONAL 0x8f
555 #define NAND_MFR_RENESAS 0x07
556 #define NAND_MFR_STMICRO 0x20
557 #define NAND_MFR_HYNIX 0xad
558 #define NAND_MFR_MICRON 0x2c
559 #define NAND_MFR_AMD 0x01
561 /**
562 * struct nand_flash_dev - NAND Flash Device ID Structure
563 * @name: Identify the device type
564 * @id: device ID code
565 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
566 * If the pagesize is 0, then the real pagesize
567 * and the eraseize are determined from the
568 * extended id bytes in the chip
569 * @erasesize: Size of an erase block in the flash device.
570 * @chipsize: Total chipsize in Mega Bytes
571 * @options: Bitfield to store chip relevant options
572 */
573 struct nand_flash_dev {
574 char *name;
575 int id;
576 unsigned long pagesize;
577 unsigned long chipsize;
578 unsigned long erasesize;
579 unsigned long options;
580 };
582 /**
583 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
584 * @name: Manufacturer name
585 * @id: manufacturer ID code of device.
586 */
587 struct nand_manufacturers {
588 int id;
589 char *name;
590 };
592 extern const struct nand_flash_dev nand_flash_ids[];
593 extern const struct nand_manufacturers nand_manuf_ids[];
595 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
596 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
597 extern int nand_default_bbt(struct mtd_info *mtd);
598 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
599 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
600 int allowbbt);
601 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
602 size_t *retlen, uint8_t *buf);
604 /*
605 * Constants for oob configuration
606 */
607 #define NAND_SMALL_BADBLOCK_POS 5
608 #define NAND_LARGE_BADBLOCK_POS 0
610 /**
611 * struct platform_nand_chip - chip level device structure
612 * @nr_chips: max. number of chips to scan for
613 * @chip_offset: chip number offset
614 * @nr_partitions: number of partitions pointed to by partitions (or zero)
615 * @partitions: mtd partition list
616 * @chip_delay: R/B delay value in us
617 * @options: Option flags, e.g. 16bit buswidth
618 * @ecclayout: ecc layout info structure
619 * @part_probe_types: NULL-terminated array of probe types
620 * @priv: hardware controller specific settings
621 */
622 struct platform_nand_chip {
623 int nr_chips;
624 int chip_offset;
625 int nr_partitions;
626 struct mtd_partition *partitions;
627 struct nand_ecclayout *ecclayout;
628 int chip_delay;
629 unsigned int options;
630 const char **part_probe_types;
631 void *priv;
632 };
634 /* Keep gcc happy */
635 struct platform_device;
637 /**
638 * struct platform_nand_ctrl - controller level device structure
639 * @hwcontrol: platform specific hardware control structure
640 * @dev_ready: platform specific function to read ready/busy pin
641 * @select_chip: platform specific chip select function
642 * @cmd_ctrl: platform specific function for controlling
643 * ALE/CLE/nCE. Also used to write command and address
644 * @priv: private data to transport driver specific settings
645 *
646 * All fields are optional and depend on the hardware driver requirements
647 */
648 struct platform_nand_ctrl {
649 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
650 int (*dev_ready)(struct mtd_info *mtd);
651 void (*select_chip)(struct mtd_info *mtd, int chip);
652 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
653 void *priv;
654 };
656 /**
657 * struct platform_nand_data - container structure for platform-specific data
658 * @chip: chip level chip structure
659 * @ctrl: controller level device structure
660 */
661 struct platform_nand_data {
662 struct platform_nand_chip chip;
663 struct platform_nand_ctrl ctrl;
664 };
666 /* Some helpers to access the data structures */
667 static inline
668 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
669 {
670 struct nand_chip *chip = mtd->priv;
672 return chip->priv;
673 }
675 /* Standard NAND functions from nand_base.c */
676 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
677 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
678 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
679 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
680 uint8_t nand_read_byte(struct mtd_info *mtd);
682 #endif /* __LINUX_MTD_NAND_H */