/* * (C) Copyright 2013 * Texas Instruments Incorporated, * * Lokesh Vutla * * Based on previous work by: * Aneesh V * Steve Sakoman * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include #include #include #include #include "mux_data.h" #ifdef CONFIG_USB_EHCI #include #include #include #endif #define CTRL_CORE_MPU_IRQ_159_REG 0x4a002b76 #define CTRL_CORE_MPU_IRQ_155_REG 0x4a002b6e #define CTRL_CORE_MPU_IRQ_154_REG 0x4a002b6c #define CTRL_CORE_MPU_IRQ_156_REG 0x4a002b70 #define CTRL_CORE_MPU_IRQ_157_REG 0x4a002b72 #define CTRL_CORE_MPU_IRQ_136_REG 0x4a002b48 #define CTRL_CORE_MPU_IRQ_141_REG 0x4a002b52 #define CTRL_CORE_MPU_IRQ_142_REG 0x4a002b54 #define CTRL_CORE_MPU_IRQ_143_REG 0x4a002b56 #define CTRL_CORE_MPU_IRQ_144_REG 0x4a002b58 #define CTRL_CORE_MPU_IRQ_145_REG 0x4a002b5a #define CTRL_CORE_MPU_IRQ_124_REG 0x4a002b34 #define CTRL_CORE_DMA_SYSTEM_DREQ_79_REG 0x4a002c16 #define CTRL_CORE_DMA_SYSTEM_DREQ_78_REG 0x4a002c14 #define CTRL_CORE_DMA_SYSTEM_DREQ_63_REG 0x4a002bf6 #define CTRL_CORE_DMA_SYSTEM_DREQ_62_REG 0x4a002bf4 DECLARE_GLOBAL_DATA_PTR; const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; /** * @brief board_init * * @return 0 */ int board_init(void) { gpmc_init(); gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ return 0; } int board_eth_init(bd_t *bis) { return 0; } /** * @brief misc_init_r - Configure EVM board specific configurations * such as power configurations, ethernet initialization as phase2 of * boot sequence * * @return 0 */ int misc_init_r(void) { return 0; } static void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) { int i; struct pad_conf_entry *pad = (struct pad_conf_entry *)array; for (i = 0; i < size; i++, pad++) writel(pad->val, base + pad->offset); } void set_muxconf_regs_essential(void) { do_set_mux32((*ctrl)->control_padconf_core_base, core_padconf_array_essential, sizeof(core_padconf_array_essential) / sizeof(struct pad_conf_entry)); } #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); omap_mmc_init(1, 0, 0, -1, -1); return 0; } #endif static void set_crossbar_mpu_irq() { /* MPU_IRQ mapping to CROSSBAR_IRQ */ writew(217, CTRL_CORE_MPU_IRQ_159_REG); /* RTC_IRQ */ writew(150, CTRL_CORE_MPU_IRQ_155_REG); /* MCASP3_IRQ_AREVT */ writew(151, CTRL_CORE_MPU_IRQ_154_REG); /* MCASP3_IRQ_AXEVT */ writew(156, CTRL_CORE_MPU_IRQ_156_REG); /* MCASP6_IRQ_AREVT */ writew(157, CTRL_CORE_MPU_IRQ_157_REG); /* MCASP6_IRQ_AXEVT */ writew(251, CTRL_CORE_MPU_IRQ_136_REG); /* MAILBOX5 */ writew(255, CTRL_CORE_MPU_IRQ_141_REG); /* MAILBOX6 */ writew(396, CTRL_CORE_MPU_IRQ_142_REG); /* IPU2 MMU */ writew(145, CTRL_CORE_MPU_IRQ_143_REG); /* DSP1 MMU1 */ writew(146, CTRL_CORE_MPU_IRQ_144_REG); /* DSP2 MMU0 */ writew(147, CTRL_CORE_MPU_IRQ_145_REG); /* DSP2 MMU1 */ writew(343, CTRL_CORE_MPU_IRQ_124_REG); /* QSPI */ } static void set_crossbar_sdma_dreq() { /* SDMA_DREQ mapping to CROSSBAR_IRQ */ writew(132, CTRL_CORE_DMA_SYSTEM_DREQ_79_REG); /* MCASP3_DREQ_RX */ writew(133, CTRL_CORE_DMA_SYSTEM_DREQ_78_REG); /* MCASP3_DREQ_TX */ writew(138, CTRL_CORE_DMA_SYSTEM_DREQ_63_REG); /* MCASP6_DREQ_RX */ writew(139, CTRL_CORE_DMA_SYSTEM_DREQ_62_REG); /* MCASP6_DREQ_TX */ } void set_crossbar_regs(void) { set_crossbar_mpu_irq(); set_crossbar_sdma_dreq(); }