index 67a071fccac5f909a2193d39350757fd14235611..c40e3355e91e7cf5ab2220e89dea39c89181d6e8 100644 (file)
--- a/README
+++ b/README
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
- CONFIG_SYS_NS16550_BROKEN_TEMT
-
- 16550 UART set the Transmitter Empty (TEMT) Bit when all output
- has finished and the transmitter is totally empty. U-Boot waits
- for this bit to be set to initialize the serial console. On some
- broken platforms this bit is not set in SPL making U-Boot to
- hang while waiting for TEMT. Define this option to avoid it.
-
- Console Interface:
Depending on board, define exactly one serial port
Define this option to include a destructive SPI flash
test ('sf test').
+ CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg
+
+ Define this option to use the Bank addr/Extended addr
+ support on SPI flashes which has size > 16Mbytes.
+
- SystemACE Support:
CONFIG_SYSTEMACE
CONFIG_SPL_LDSCRIPT
LDSCRIPT for linking the SPL binary.
+ CONFIG_SPL_MAX_FOOTPRINT
+ Maximum size in memory allocated to the SPL, BSS included.
+ When defined, the linker checks that the actual memory
+ used by SPL from _start to __bss_end does not exceed it.
+ CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
+ must not be both defined at the same time.
+
CONFIG_SPL_MAX_SIZE
- Maximum binary size (text, data and rodata) of the SPL binary.
+ Maximum size of the SPL image (text, data, rodata, and
+ linker lists sections), BSS excluded.
+ When defined, the linker checks that the actual size does
+ not exceed it.
CONFIG_SPL_TEXT_BASE
TEXT_BASE for linking the SPL binary.
Link address for the BSS within the SPL binary.
CONFIG_SPL_BSS_MAX_SIZE
- Maximum binary size of the BSS section of the SPL binary.
+ Maximum size in memory allocated to the SPL BSS.
+ When defined, the linker checks that the actual memory used
+ by SPL from __bss_start to __bss_end does not exceed it.
+ CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
+ must not be both defined at the same time.
CONFIG_SPL_STACK
Adress of the start of the stack SPL will use
Support for lib/libgeneric.o in SPL binary
CONFIG_SPL_PAD_TO
- Linker address to which the SPL should be padded before
- appending the SPL payload.
+ Image offset to which the SPL should be padded before appending
+ the SPL payload. By default, this is defined as
+ CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
+ CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
+ payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
directly. You should not need to touch this setting.
+- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
+ This is set by OMAP boards for the max time that reset should
+ be asserted. See doc/README.omap-reset-time for details on how
+ the value can be calulated on a given board.
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
- CONFIG_SYS_SRIOn_MEM_SIZE:
Size of SRIO port 'n' memory region
-- CONFIG_SYS_NDFC_16
- Defined to tell the NDFC that the NAND chip is using a
- 16 bit bus.
+- CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ Defined to tell the NAND controller that the NAND chip is using
+ a 16 bit bus.
+ Not all NAND drivers use this symbol.
+ Example of drivers that use it:
+ - drivers/mtd/nand/ndfc.c
+ - drivers/mtd/nand/mxc_nand.c
- CONFIG_SYS_NDFC_EBC0_CFG
Sets the EBC0_CFG register for the NDFC. If not defined