HACK: ARM: DRA7xx: crossbar: Add support for crossbar

[glsdk/glsdk-u-boot.git] / arch / arm / cpu / armv7 / omap-common / hwinit-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 60af7eb9b0d7589e5a3aa8dd913b9020195871f3..61cc99c6f79c6453ee48857d3603dc5674952a0c 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -34,6 +34,12 @@
 #include <asm/emif.h>
 #include <asm/omap_common.h>
 #include <linux/compiler.h>
+#include <asm/cache.h>
+#include <asm/system.h>
+
+#define ARMV7_DCACHE_WRITEBACK  0xe
+#define        ARMV7_DOMAIN_CLIENT     1
+#define ARMV7_DOMAIN_MASK      (0x3 << 0)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -81,20 +87,20 @@ u32 cortex_rev(void)
 void omap_rev_string(void)
 {
        u32 omap_rev = omap_revision();
+       u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
        u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
        u32 major_rev = (omap_rev & 0x00000F00) >> 8;
        u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
 
-       printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
-               minor_rev);
+       if (soc_variant)
+               printf("OMAP");
+       else
+               printf("DRA");
+       printf("%x ES%x.%x\n", omap_variant, major_rev,
+              minor_rev);
 }
 
 #ifdef CONFIG_SPL_BUILD
-static void init_boot_params(void)
-{
-       boot_params_ptr = (u32 *) &boot_params;
-}
-
 void spl_display_print(void)
 {
        omap_rev_string();
@@ -105,6 +111,57 @@ void __weak srcomp_enable(void)
 {
 }
 
+static void save_omap_boot_params(void)
+{
+       u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+       u8 boot_device;
+       u32 dev_desc, dev_data;
+
+       if ((rom_params <  NON_SECURE_SRAM_START) ||
+           (rom_params > NON_SECURE_SRAM_END))
+               return;
+
+       /*
+        * rom_params can be type casted to omap_boot_parameters and
+        * used. But it not correct to assume that romcode structure
+        * encoding would be same as u-boot. So use the defined offsets.
+        */
+       gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+                                  *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+       gd->arch.omap_boot_params.ch_flags =
+                               *((u8 *)(rom_params + CH_FLAGS_OFFSET));
+
+       if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+           (boot_device <= MMC_BOOT_DEVICES_END)) {
+               if ((omap_hw_init_context() ==
+                                     OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+                       gd->arch.omap_boot_params.omap_bootmode =
+                       *((u8 *)(rom_params + BOOT_MODE_OFFSET));
+               } else {
+                       dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+                       dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+                       gd->arch.omap_boot_params.omap_bootmode =
+                                       *((u32 *)(dev_data + BOOT_MODE_OFFSET));
+               }
+       }
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+       save_omap_boot_params();
+       return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+void __weak set_crossbar_regs(void)
+{
+}
+
 /*
  * Routine: s_init
  * Description: Does early system init of watchdog, muxing,  andclocks
@@ -121,6 +178,14 @@ void __weak srcomp_enable(void)
  */
 void s_init(void)
 {
+       /*
+        * Save the boot parameters passed from romcode.
+        * We cannot delay the saving further than this,
+        * to prevent overwrites.
+        */
+#ifdef CONFIG_SPL_BUILD
+       save_omap_boot_params();
+#endif
        init_omap_revision();
        hw_data_init();
 
@@ -141,11 +206,11 @@ void s_init(void)
 #endif
        prcm_init();
 #ifdef CONFIG_SPL_BUILD
-       timer_init();
-
        /* For regular u-boot sdram_init() is called from dram_init() */
        sdram_init();
-       init_boot_params();
+#endif
+#ifndef CONFIG_SPL_BUILD
+       set_crossbar_regs();
 #endif
 }
 
@@ -264,4 +329,33 @@ void enable_caches(void)
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
 }
+
+void dram_bank_mmu_setup(int bank)
+{
+       bd_t *bd = gd->bd;
+       int     i;
+
+       u32 start = bd->bi_dram[bank].start >> 20;
+       u32 size = bd->bi_dram[bank].size >> 20;
+       u32 end = start + size;
+
+       debug("%s: bank: %d\n", __func__, bank);
+       for (i = start; i < end; i++)
+               set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+
+}
+
+void arm_init_domains(void)
+{
+       u32 reg;
+
+       reg = get_dacr();
+       /*
+       * Set DOMAIN to client access so that all permissions
+       * set in pagetables are validated by the mmu.
+       */
+       reg &= ~ARMV7_DOMAIN_MASK;
+       reg |= ARMV7_DOMAIN_CLIENT;
+       set_dacr(reg);
+}
 #endif