diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index cf71ab444382c7179982eb02a44ab798c6a397a0..61cc99c6f79c6453ee48857d3603dc5674952a0c 100644 (file)
* MA 02111-1307 USA
*/
#include <common.h>
+#include <spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
+#include <linux/compiler.h>
+#include <asm/cache.h>
+#include <asm/system.h>
+
+#define ARMV7_DCACHE_WRITEBACK 0xe
+#define ARMV7_DOMAIN_CLIENT 1
+#define ARMV7_DOMAIN_MASK (0x3 << 0)
DECLARE_GLOBAL_DATA_PTR;
void omap_rev_string(void)
{
u32 omap_rev = omap_revision();
+ u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
- printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
- minor_rev);
+ if (soc_variant)
+ printf("OMAP");
+ else
+ printf("DRA");
+ printf("%x ES%x.%x\n", omap_variant, major_rev,
+ minor_rev);
}
#ifdef CONFIG_SPL_BUILD
-static void init_boot_params(void)
+void spl_display_print(void)
{
- boot_params_ptr = (u32 *) &boot_params;
+ omap_rev_string();
}
#endif
+void __weak srcomp_enable(void)
+{
+}
+
+static void save_omap_boot_params(void)
+{
+ u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+ u8 boot_device;
+ u32 dev_desc, dev_data;
+
+ if ((rom_params < NON_SECURE_SRAM_START) ||
+ (rom_params > NON_SECURE_SRAM_END))
+ return;
+
+ /*
+ * rom_params can be type casted to omap_boot_parameters and
+ * used. But it not correct to assume that romcode structure
+ * encoding would be same as u-boot. So use the defined offsets.
+ */
+ gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+ *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+ gd->arch.omap_boot_params.ch_flags =
+ *((u8 *)(rom_params + CH_FLAGS_OFFSET));
+
+ if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+ (boot_device <= MMC_BOOT_DEVICES_END)) {
+ if ((omap_hw_init_context() ==
+ OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+ gd->arch.omap_boot_params.omap_bootmode =
+ *((u8 *)(rom_params + BOOT_MODE_OFFSET));
+ } else {
+ dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+ dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+ gd->arch.omap_boot_params.omap_bootmode =
+ *((u32 *)(dev_data + BOOT_MODE_OFFSET));
+ }
+ }
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+ save_omap_boot_params();
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+void __weak set_crossbar_regs(void)
+{
+}
+
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
*/
void s_init(void)
{
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+#ifdef CONFIG_SPL_BUILD
+ save_omap_boot_params();
+#endif
init_omap_revision();
+ hw_data_init();
+
+#ifdef CONFIG_SPL_BUILD
+ if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+ force_emif_self_refresh();
+#endif
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
+ srcomp_enable();
setup_clocks_for_console();
+
+ gd = &gdata;
+
preloader_console_init();
do_io_settings();
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
- timer_init();
-
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
- init_boot_params();
+#endif
+#ifndef CONFIG_SPL_BUILD
+ set_crossbar_regs();
#endif
}
*/
u32 omap_sdram_size(void)
{
- u32 section, i, total_size = 0, size, addr;
+ u32 section, i, valid;
+ u64 sdram_start = 0, sdram_end = 0, addr,
+ size, total_size = 0, trap_size = 0;
for (i = 0; i < 4; i++) {
section = __raw_readl(DMM_BASE + i*4);
+ valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
+ (EMIF_SDRC_ADDRSPC_SHIFT);
addr = section & EMIF_SYS_ADDR_MASK;
+
/* See if the address is valid */
if ((addr >= DRAM_ADDR_SPACE_START) &&
(addr < DRAM_ADDR_SPACE_END)) {
EMIF_SYS_SIZE_SHIFT);
size = 1 << size;
size *= SZ_16M;
- total_size += size;
+
+ if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
+ if (!sdram_start || (addr < sdram_start))
+ sdram_start = addr;
+ if (!sdram_end || ((addr + size) > sdram_end))
+ sdram_end = addr + size;
+ } else {
+ trap_size = size;
+ }
+
}
+
}
+ total_size = (sdram_end - sdram_start) - (trap_size);
return total_size;
}
*/
u32 get_device_type(void)
{
- struct omap_sys_ctrl_regs *ctrl =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- return (readl(&ctrl->control_status) &
+ return (readl((*ctrl)->control_status) &
(DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
}
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
+
+void dram_bank_mmu_setup(int bank)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ u32 start = bd->bi_dram[bank].start >> 20;
+ u32 size = bd->bi_dram[bank].size >> 20;
+ u32 end = start + size;
+
+ debug("%s: bank: %d\n", __func__, bank);
+ for (i = start; i < end; i++)
+ set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+
+}
+
+void arm_init_domains(void)
+{
+ u32 reg;
+
+ reg = get_dacr();
+ /*
+ * Set DOMAIN to client access so that all permissions
+ * set in pagetables are validated by the mmu.
+ */
+ reg &= ~ARMV7_DOMAIN_MASK;
+ reg |= ARMV7_DOMAIN_CLIENT;
+ set_dacr(reg);
+}
#endif