ARM: DRA7xx: Enable GMAC clock control

[glsdk/glsdk-u-boot.git] / arch / arm / cpu / armv7 / omap5 / prcm-regs.c

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index b8a61fe8813fd6f1bac8fd55a273dfa847f89278..091338397e8f878a5e355a8861ae8901e5b2781f 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -311,6 +311,7 @@ struct prcm_regs const omap5_es1_prcm = {
 
 struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_status                         = 0x4A002134,
+       .control_padconf_core_base              = 0x4A002800,
        .control_paconf_global                  = 0x4A002DA0,
        .control_paconf_mode                    = 0x4A002DA4,
        .control_smart1io_padconf_0             = 0x4A002DA8,
@@ -358,6 +359,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_port_emif2_sdram_config        = 0x4AE0C118,
        .control_emif1_sdram_config_ext         = 0x4AE0C144,
        .control_emif2_sdram_config_ext         = 0x4AE0C148,
+       .control_padconf_wkup_base              = 0x4AE0C800,
        .control_smart1nopmio_padconf_0         = 0x4AE0CDA0,
        .control_smart1nopmio_padconf_1         = 0x4AE0CDA4,
        .control_padconf_mode                   = 0x4AE0CDA8,
@@ -434,6 +436,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_srcomp_east_side               = 0x4A002E7C,
        .control_srcomp_west_side               = 0x4A002E80,
        .control_srcomp_code_latch              = 0x4A002E84,
+       .control_ddr_control_ext_0              = 0x4A002E88,
        .control_padconf_core_base              = 0x4A003400,
        .control_port_emif1_sdram_config        = 0x4AE0C110,
        .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
@@ -729,6 +732,7 @@ struct prcm_regs const omap5_es2_prcm = {
        .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
        .prm_rstctrl = 0x4ae07c00,
        .prm_rstst = 0x4ae07c04,
+       .prm_rsttime = 0x4ae07c08,
        .prm_vc_val_bypass = 0x4ae07ca0,
        .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
        .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
@@ -794,6 +798,7 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_ssc_deltamstep_dpll_ddrphy          = 0x4a00522c,
        .cm_clkmode_dpll_dsp                    = 0x4a005234,
        .cm_shadow_freq_config1                 = 0x4a005260,
+       .cm_clkmode_dpll_gmac                   = 0x4a0052a8,
 
        /* cm1.mpu */
        .cm_mpu_mpu_clkctrl                     = 0x4a005320,
@@ -891,6 +896,8 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_l3init_hsusbhost_clkctrl            = 0x4a009340,
        .cm_l3init_hsusbotg_clkctrl             = 0x4a009348,
        .cm_l3init_hsusbtll_clkctrl             = 0x4a009350,
+       .cm_gmac_clkstctrl                      = 0x4a0093c0,
+       .cm_gmac_gmac_clkctrl                   = 0x4a0093d0,
        .cm_l3init_ocp2scp1_clkctrl             = 0x4a0093e0,
 
        /* cm2.l4per */
@@ -922,6 +929,7 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_l4per_gpio8_clkctrl                 = 0x4a009818,
        .cm_l4per_mmcsd3_clkctrl                = 0x4a009820,
        .cm_l4per_mmcsd4_clkctrl                = 0x4a009828,
+       .cm_l4per_qspi_clkctrl                  = 0x4a009838,
        .cm_l4per_uart1_clkctrl                 = 0x4a009840,
        .cm_l4per_uart2_clkctrl                 = 0x4a009848,
        .cm_l4per_uart3_clkctrl                 = 0x4a009850,
@@ -940,6 +948,7 @@ struct prcm_regs const dra7xx_prcm = {
        /* l4 wkup regs */
        .cm_abe_pll_ref_clksel                  = 0x4ae0610c,
        .cm_sys_clksel                          = 0x4ae06110,
+       .cm_abe_pll_sys_clksel                  = 0x4ae06118,
        .cm_wkup_clkstctrl                      = 0x4ae07800,
        .cm_wkup_l4wkup_clkctrl                 = 0x4ae07820,
        .cm_wkup_wdtimer1_clkctrl               = 0x4ae07828,
@@ -952,6 +961,7 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_wkupaon_scrm_clkctrl                = 0x4ae07890,
        .prm_rstctrl                            = 0x4ae07d00,
        .prm_rstst                              = 0x4ae07d04,
+       .prm_rsttime                            = 0x4ae07d08,
        .prm_vc_val_bypass                      = 0x4ae07da0,
        .prm_vc_cfg_i2c_mode                    = 0x4ae07db4,
        .prm_vc_cfg_i2c_clk                     = 0x4ae07db8,