index 91618d3d8aea21e0b26365f1f7cb68f75032437b..e8f4c19d4908c9d208c0eb6259f53dfef11d4ad7 100644 (file)
* MA 02111-1307 USA
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
-inline void lowlevel_init(void) {}
+void lowlevel_init(void)
+{
+ zynq_slcr_unlock();
+ /* remap DDR to zero, FILTERSTART */
+ writel(0, &scu_base->filter_start);
+
+ /* Device config APB, unlock the PCAP */
+ writel(0x757BDF0D, &devcfg_base->unlock);
+ writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+
+ /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+ writel(0x1F, &slcr_base->ocm_cfg);
+ /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+ writel(0x0, &slcr_base->fpga_rst_ctrl);
+ /* TZ_DDR_RAM, Set DDR trust zone non-secure */
+ writel(0xFFFFFFFF, &slcr_base->trust_zone);
+ /* Set urgent bits with register */
+ writel(0x0, &slcr_base->ddr_urgent_sel);
+ /* Urgent write, ports S2/S3 */
+ writel(0xC, &slcr_base->ddr_urgent);
+
+ zynq_slcr_lock();
+}
void reset_cpu(ulong addr)
{