ARM: DRA7xx: Add CPSW support to DRA7xx EVM

[glsdk/glsdk-u-boot.git] / arch / arm / include / asm / arch-omap5 / cpu.h

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 0697a732de44ae043177cdf73e6981b8c7af3e5c..347f104e80e3af6815c19ba6ccc8eb159962c1cc 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -116,21 +116,11 @@ struct watchdog {
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
+#define BIT(x)                         (1 << (x))
+
 #define WD_UNLOCK1             0xAAAA
 #define WD_UNLOCK2             0x5555
 
-#define SYSCLKDIV_1            (0x1 << 6)
-#define SYSCLKDIV_2            (0x1 << 7)
-
-#define CLKSEL_GPT1            (0x1 << 0)
-
-#define EN_GPT1                        (0x1 << 0)
-#define EN_32KSYNC             (0x1 << 2)
-
-#define ST_WDT2                        (0x1 << 5)
-
-#define RESETDONE              (0x1 << 0)
-
 #define TCLR_ST                        (0x1 << 0)
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
@@ -142,6 +132,8 @@ struct watchdog {
 #define I2C_BASE1              (OMAP54XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2              (OMAP54XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3              (OMAP54XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4              (OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5              (OMAP54XX_L4_PER_BASE + 0x7C000)
 
 /* MUSB base */
 #define MUSB_BASE              (OMAP54XX_L4_CORE_BASE + 0xAB000)
@@ -172,4 +164,21 @@ struct watchdog {
 #define OMAP_GPIO_CLEARDATAOUT         0x0190
 #define OMAP_GPIO_SETDATAOUT           0x0194
 
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE               0x4AE06000
+#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL            PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET      0x01
+#define PRM_RSTST              (PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK      0x7FEA
+
+/* DRA7XX CPSW Config space */
+#define CPSW_BASE                      0x48484000
+#define CPSW_MDIO_BASE                 0x48485000
+
 #endif /* _CPU_H */