ARM: DRA7xx: Add CPSW support to DRA7xx EVM

[glsdk/glsdk-u-boot.git] / arch / arm / include / asm / arch-omap5 / omap.h

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index d2c493011d1680b4f9bc9d65675492fab698f3c9..3076a5ec89f550e17049a5bfb991d0baf58b8ab3 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -180,6 +180,27 @@ struct s32ktimer {
 #define SRCODE_OVERRIDE_SEL_XS_SHIFT   0
 #define SRCODE_OVERRIDE_SEL_XS_MASK    (1 << 0)
 
+/* IO Delay module defines */
+#define CFG_IO_DELAY_BASE              0x4844A000
+#define CFG_IO_DELAY_LOCK              (CFG_IO_DELAY_BASE + 0x02C)
+
+/* CPSW IO Delay registers*/
+#define CFG_RGMII0_TXCTL               (CFG_IO_DELAY_BASE + 0x74C)
+#define CFG_RGMII0_TXD0                        (CFG_IO_DELAY_BASE + 0x758)
+#define CFG_RGMII0_TXD1                        (CFG_IO_DELAY_BASE + 0x764)
+#define CFG_RGMII0_TXD2                        (CFG_IO_DELAY_BASE + 0x770)
+#define CFG_RGMII0_TXD3                        (CFG_IO_DELAY_BASE + 0x77C)
+#define CFG_VIN2A_D13                  (CFG_IO_DELAY_BASE + 0xA7C)
+#define CFG_VIN2A_D17                  (CFG_IO_DELAY_BASE + 0xAAC)
+#define CFG_VIN2A_D16                  (CFG_IO_DELAY_BASE + 0xAA0)
+#define CFG_VIN2A_D15                  (CFG_IO_DELAY_BASE + 0xA94)
+#define CFG_VIN2A_D14                  (CFG_IO_DELAY_BASE + 0xA88)
+
+#define CFG_IO_DELAY_UNLOCK_KEY                0x0000AAAA
+#define CFG_IO_DELAY_LOCK_KEY          0x0000AAAB
+#define CFG_IO_DELAY_ACCESS_PATTERN    0x00029000
+#define CFG_IO_DELAY_LOCK_MASK         0x400
+
 #ifndef __ASSEMBLY__
 struct srcomp_params {
        s8 divide_factor;
@@ -196,5 +217,10 @@ struct ctrl_ioregs {
        u32 ctrl_emif_sdram_config_ext;
        u32 ctrl_ddr_ctrl_ext_0;
 };
+
+struct io_delay {
+       u32 addr;
+       u32 dly;
+};
 #endif /* __ASSEMBLY__ */
 #endif