index c2d8388b32c7a8fb98c7506af5ed0abba5f8322f..8a886ec9383ab580143c861cf63522e9a7a19ed2 100644 (file)
u32 cm_div_h12_dpll_core;
u32 cm_div_h13_dpll_core;
u32 cm_div_h14_dpll_core;
+ u32 cm_div_h21_dpll_core;
+ u32 cm_div_h24_dpll_core;
u32 cm_ssc_deltamstep_dpll_core;
u32 cm_ssc_modfreqdiv_dpll_core;
u32 cm_emu_override_dpll_core;
u32 cm_div_m3_dpll_per;
u32 cm_div_h11_dpll_per;
u32 cm_div_h12_dpll_per;
+ u32 cm_div_h13_dpll_per;
u32 cm_div_h14_dpll_per;
u32 cm_ssc_deltamstep_dpll_per;
u32 cm_ssc_modfreqdiv_dpll_per;
u32 prm_vc_cfg_channel;
};
+struct omap_sys_ctrl_regs {
+ u32 control_status;
+ u32 control_id_code;
+ u32 control_std_fuse_opp_bgap;
+ u32 control_ldosram_iva_voltage_ctrl;
+ u32 control_ldosram_mpu_voltage_ctrl;
+ u32 control_ldosram_core_voltage_ctrl;
+ u32 control_paconf_global;
+ u32 control_paconf_mode;
+ u32 control_smart1io_padconf_0;
+ u32 control_smart1io_padconf_1;
+ u32 control_smart1io_padconf_2;
+ u32 control_smart2io_padconf_0;
+ u32 control_smart2io_padconf_1;
+ u32 control_smart2io_padconf_2;
+ u32 control_smart3io_padconf_0;
+ u32 control_smart3io_padconf_1;
+ u32 control_pbias;
+ u32 control_i2c_0;
+ u32 control_camera_rx;
+ u32 control_hdmi_tx_phy;
+ u32 control_uniportm;
+ u32 control_dsiphy;
+ u32 control_mcbsplp;
+ u32 control_usb2phycore;
+ u32 control_hdmi_1;
+ u32 control_hsi;
+ u32 control_ddr3ch1_0;
+ u32 control_ddr3ch2_0;
+ u32 control_ddrch1_0;
+ u32 control_ddrch1_1;
+ u32 control_ddrch2_0;
+ u32 control_ddrch2_1;
+ u32 control_lpddr2ch1_0;
+ u32 control_lpddr2ch1_1;
+ u32 control_ddrio_0;
+ u32 control_ddrio_1;
+ u32 control_ddrio_2;
+ u32 control_lpddr2io1_0;
+ u32 control_lpddr2io1_1;
+ u32 control_lpddr2io1_2;
+ u32 control_lpddr2io1_3;
+ u32 control_lpddr2io2_0;
+ u32 control_lpddr2io2_1;
+ u32 control_lpddr2io2_2;
+ u32 control_lpddr2io2_3;
+ u32 control_hyst_1;
+ u32 control_usbb_hsic_control;
+ u32 control_c2c;
+ u32 control_core_control_spare_rw;
+ u32 control_core_control_spare_r;
+ u32 control_core_control_spare_r_c0;
+ u32 control_srcomp_north_side;
+ u32 control_srcomp_south_side;
+ u32 control_srcomp_east_side;
+ u32 control_srcomp_west_side;
+ u32 control_srcomp_code_latch;
+ u32 control_pbiaslite;
+ u32 control_port_emif1_sdram_config;
+ u32 control_port_emif1_lpddr2_nvm_config;
+ u32 control_port_emif2_sdram_config;
+ u32 control_emif1_sdram_config_ext;
+ u32 control_emif2_sdram_config_ext;
+ u32 control_smart1nopmio_padconf_0;
+ u32 control_smart1nopmio_padconf_1;
+ u32 control_padconf_mode;
+ u32 control_xtal_oscillator;
+ u32 control_i2c_2;
+ u32 control_ckobuffer;
+ u32 control_wkup_control_spare_rw;
+ u32 control_wkup_control_spare_r;
+ u32 control_wkup_control_spare_r_c0;
+ u32 control_srcomp_east_side_wkup;
+ u32 control_efuse_1;
+ u32 control_efuse_2;
+ u32 control_efuse_3;
+ u32 control_efuse_4;
+ u32 control_efuse_5;
+ u32 control_efuse_6;
+ u32 control_efuse_7;
+ u32 control_efuse_8;
+ u32 control_efuse_9;
+ u32 control_efuse_10;
+ u32 control_efuse_11;
+ u32 control_efuse_12;
+ u32 control_efuse_13;
+};
+
struct dpll_params {
u32 m;
u32 n;
s8 m5_h12;
s8 m6_h13;
s8 m7_h14;
+ s8 h21;
s8 h22;
s8 h23;
+ s8 h24;
};
struct dpll_regs {
u32 cm_div_m5_h12_dpll;
u32 cm_div_m6_h13_dpll;
u32 cm_div_m7_h14_dpll;
- u32 reserved[3];
+ u32 reserved[2];
+ u32 cm_div_h21_dpll;
u32 cm_div_h22_dpll;
u32 cm_div_h23_dpll;
+ u32 cm_div_h24_dpll;
};
struct dplls {
const struct dpll_params *usb;
};
+struct pmic_data {
+ u32 base_offset;
+ u32 step;
+ u32 start_code;
+ unsigned gpio;
+ int gpio_en;
+};
+
+struct volts {
+ u32 value;
+ u32 addr;
+ struct pmic_data *pmic;
+};
+
+struct vcores_data {
+ struct volts mpu;
+ struct volts core;
+ struct volts mm;
+};
+
extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm;
+extern struct prcm_regs const omap5_es2_prcm;
extern struct prcm_regs const omap4_prcm;
extern struct dplls const **dplls_data;
+extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
+extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const omap4_ctrl;
+extern struct omap_sys_ctrl_regs const omap5_ctrl;
void hw_data_init(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
+void scale_vcores(struct vcores_data const *);
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
/* Max value for DPLL multiplier M */
#define OMAP_DPLL_MAX_N 127
#define OMAP5430_SILICON_ID_INVALID 0
#define OMAP5430_ES1_0 0x54300100
#define OMAP5432_ES1_0 0x54320100
+#define OMAP5430_ES2_0 0x54300200
+#define OMAP5432_ES2_0 0x54320200
#endif /* _OMAP_COMMON_H_ */