index 6b28f2e3f756d478b3db2e62c1d03866159cf2d6..9c1a154125e405ce6e27017cbf4f09bb4dbd1367 100644 (file)
#include <common.h>
-#define NUM_SYS_CLKS 8
+#define NUM_SYS_CLKS 7
struct prcm_regs {
/* cm1.ckgen */
u32 cm_ssc_deltamstep_dpll_ddrphy;
u32 cm_clkmode_dpll_dsp;
u32 cm_shadow_freq_config1;
+ u32 cm_clkmode_dpll_gmac;
u32 cm_mpu_mpu_clkctrl;
/* cm1.dsp */
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
/* l4 wkup regs */
u32 cm_abe_pll_ref_clksel;
u32 cm_sys_clksel;
+ u32 cm_abe_pll_sys_clksel;
u32 cm_wkup_clkstctrl;
u32 cm_wkup_l4wkup_clkctrl;
u32 cm_wkup_wdtimer1_clkctrl;
u32 control_ddrio_0;
u32 control_ddrio_1;
u32 control_ddrio_2;
+ u32 control_ddr_control_ext_0;
u32 control_lpddr2io1_0;
u32 control_lpddr2io1_1;
u32 control_lpddr2io1_2;
const struct dpll_params *iva;
const struct dpll_params *usb;
const struct dpll_params *ddr;
+ const struct dpll_params *gmac;
};
struct pmic_data {
int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
};
+/**
+ * struct volts_efuse_data - efuse definition for voltage
+ * @reg: register address for efuse
+ * @reg_bits: Number of bits in a register address, mandatory.
+ */
+struct volts_efuse_data {
+ u32 reg;
+ u8 reg_bits;
+};
+
struct volts {
u32 value;
u32 addr;
+ struct volts_efuse_data efuse;
struct pmic_data *pmic;
};
extern u32 *const omap_si_rev;
return *omap_si_rev;
}
+
+#define OMAP54xx 0x54000000
+
+static inline u8 is_omap54xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
+}
#endif
/*