index 091ddb508d5673bb493e76ec255d7ce8de284413..d9f9c33118bb927c33d3580713ab65493c7cafba 100644 (file)
#ifndef _OMAP_COMMON_H_
#define _OMAP_COMMON_H_
+#ifndef __ASSEMBLY__
+
#include <common.h>
-#define NUM_SYS_CLKS 8
+#define NUM_SYS_CLKS 7
struct prcm_regs {
/* cm1.ckgen */
u32 cm_ssc_deltamstep_dpll_ddrphy;
u32 cm_clkmode_dpll_dsp;
u32 cm_shadow_freq_config1;
+ u32 cm_clkmode_dpll_gmac;
u32 cm_mpu_mpu_clkctrl;
/* cm1.dsp */
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
/* l4 wkup regs */
u32 cm_abe_pll_ref_clksel;
u32 cm_sys_clksel;
+ u32 cm_abe_pll_sys_clksel;
u32 cm_wkup_clkstctrl;
u32 cm_wkup_l4wkup_clkctrl;
u32 cm_wkup_wdtimer1_clkctrl;
u32 cm_wkupaon_io_srcomp_clkctrl;
u32 prm_rstctrl;
u32 prm_rstst;
+ u32 prm_rsttime;
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
u32 cm_l3init_usbphy_clkctrl;
u32 cm_l4per_mcbsp4_clkctrl;
u32 prm_vc_cfg_channel;
+
+ /* GMAC Clk Ctrl */
+ u32 cm_gmac_gmac_clkctrl;
+ u32 cm_gmac_clkstctrl;
};
struct omap_sys_ctrl_regs {
u32 control_ldosram_iva_voltage_ctrl;
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
+ u32 control_usbotghs_ctrl;
u32 control_padconf_core_base;
u32 control_paconf_global;
u32 control_paconf_mode;
u32 control_ddrio_0;
u32 control_ddrio_1;
u32 control_ddrio_2;
+ u32 control_ddr_control_ext_0;
u32 control_lpddr2io1_0;
u32 control_lpddr2io1_1;
u32 control_lpddr2io1_2;
const struct dpll_params *iva;
const struct dpll_params *usb;
const struct dpll_params *ddr;
+ const struct dpll_params *gmac;
};
struct pmic_data {
u32 start_code;
unsigned gpio;
int gpio_en;
+ u32 i2c_slave_addr;
+ void (*pmic_bus_init)(void);
+ int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
+};
+
+/**
+ * struct volts_efuse_data - efuse definition for voltage
+ * @reg: register address for efuse
+ * @reg_bits: Number of bits in a register address, mandatory.
+ */
+struct volts_efuse_data {
+ u32 reg;
+ u8 reg_bits;
};
struct volts {
u32 value;
u32 addr;
+ struct volts_efuse_data efuse;
struct pmic_data *pmic;
};
struct volts mpu;
struct volts core;
struct volts mm;
+ struct volts gpu;
+ struct volts eve;
+ struct volts iva;
};
extern struct prcm_regs const **prcm;
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
-/* Max value for DPLL multiplier M */
-#define OMAP_DPLL_MAX_N 127
-
/* HW Init Context */
#define OMAP_INIT_CONTEXT_SPL 0
#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1
return *omap_si_rev;
}
+#define OMAP54xx 0x54000000
+
+static inline u8 is_omap54xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
+}
+#endif
+
/*
* silicon revisions.
* Moving this to common, so that most of code can be moved to common,
/* DRA7XX */
#define DRA752_ES1_0 0x07520100
+
+/*
+ * SRAM scratch space entries
+ */
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
+#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
+#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+
#endif /* _OMAP_COMMON_H_ */