ppc4xx: TLB init file cleanup

[glsdk/glsdk-u-boot.git] / board / sandburst / metrobox / init.S

diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S
index ccdec46ee54f85bd1aa7d7f3b5d8b42bb59cf0f9..fa78a3f4ba02d586c5b034f0ea13ef5dce0a4a57 100644 (file)
--- a/board/sandburst/metrobox/init.S
+++ b/board/sandburst/metrobox/init.S
@@ -22,55 +22,9 @@
 */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -87,13 +41,13 @@
 
 tlbtab:
        tlbtab_start
-       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
        tlbtab_end