Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[glsdk/glsdk-u-boot.git] / board / ti / beagle / beagle.c

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index f20ebed4524298c4d5bb777dd732f7ae509d1b1c..b829a792b2c49b06e04508ce3b2bf9b4f3eb225a 100644 (file)
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -144,8 +144,7 @@ static int get_board_revision(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
        int pop_mfr, pop_id;
 
@@ -156,29 +155,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
         */
        identify_nand_chip(&pop_mfr, &pop_id);
 
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
        switch (get_board_revision()) {
        case REVISION_C4:
                if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
                        /* 512MB DDR */
-                       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-                       *ctrla = NUMONYX_V_ACTIMA_165;
-                       *ctrlb = NUMONYX_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+                       timings->ctrla = NUMONYX_V_ACTIMA_165;
+                       timings->ctrlb = NUMONYX_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                        break;
                } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
                        /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
-                       *mcfg = MICRON_V_MCFG_165(128 << 20);
-                       *ctrla = MICRON_V_ACTIMA_165;
-                       *ctrlb = MICRON_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_165;
+                       timings->ctrlb = MICRON_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                        break;
                } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
                        /* Beagleboard Rev C5, 256MB DDR */
-                       *mcfg = MICRON_V_MCFG_200(256 << 20);
-                       *ctrla = MICRON_V_ACTIMA_200;
-                       *ctrlb = MICRON_V_ACTIMB_200;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+                       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_200;
+                       timings->ctrlb = MICRON_V_ACTIMB_200;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                        break;
                }
        case REVISION_XM_A:
@@ -186,24 +185,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
        case REVISION_XM_C:
                if (pop_mfr == 0) {
                        /* 256MB DDR */
-                       *mcfg = MICRON_V_MCFG_200(256 << 20);
-                       *ctrla = MICRON_V_ACTIMA_200;
-                       *ctrlb = MICRON_V_ACTIMB_200;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+                       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_200;
+                       timings->ctrlb = MICRON_V_ACTIMB_200;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                } else {
                        /* 512MB DDR */
-                       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-                       *ctrla = NUMONYX_V_ACTIMA_165;
-                       *ctrlb = NUMONYX_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+                       timings->ctrla = NUMONYX_V_ACTIMA_165;
+                       timings->ctrlb = NUMONYX_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                }
                break;
        default:
                /* Assume 128MB and Micron/165MHz timings to be safe */
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
        }
 }
 #endif