diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 7bbb5492feb1110dacfd6178170218fc794c76fa..8214a7acb4a906784092b414df902c5ed3c69591 100644 (file)
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
* MA 02111-1307 USA
*/
#include <common.h>
* MA 02111-1307 USA
*/
#include <common.h>
-#include <twl6035.h>
+#include <palmas.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/ehci-omap.h>
#endif
#include <asm/ehci-omap.h>
#endif
+#define CTRL_CORE_MPU_IRQ_159_REG 0x4a002b76
+#define CTRL_CORE_MPU_IRQ_155_REG 0x4a002b6e
+#define CTRL_CORE_MPU_IRQ_154_REG 0x4a002b6c
+#define CTRL_CORE_MPU_IRQ_156_REG 0x4a002b70
+#define CTRL_CORE_MPU_IRQ_157_REG 0x4a002b72
+#define CTRL_CORE_MPU_IRQ_136_REG 0x4a002b48
+#define CTRL_CORE_MPU_IRQ_141_REG 0x4a002b52
+#define CTRL_CORE_MPU_IRQ_142_REG 0x4a002b54
+#define CTRL_CORE_MPU_IRQ_143_REG 0x4a002b56
+#define CTRL_CORE_MPU_IRQ_144_REG 0x4a002b58
+#define CTRL_CORE_MPU_IRQ_145_REG 0x4a002b5a
+#define CTRL_CORE_MPU_IRQ_124_REG 0x4a002b34
+
+#define CTRL_CORE_DMA_SYSTEM_DREQ_79_REG 0x4a002c16
+#define CTRL_CORE_DMA_SYSTEM_DREQ_78_REG 0x4a002c14
+#define CTRL_CORE_DMA_SYSTEM_DREQ_63_REG 0x4a002bf6
+#define CTRL_CORE_DMA_SYSTEM_DREQ_62_REG 0x4a002bf4
+
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
return 0;
}
#endif
return 0;
}
#endif
+
+static void set_crossbar_mpu_irq()
+{
+ /* MPU_IRQ mapping to CROSSBAR_IRQ */
+ writew(217, CTRL_CORE_MPU_IRQ_159_REG); /* RTC_IRQ */
+ writew(150, CTRL_CORE_MPU_IRQ_155_REG); /* MCASP3_IRQ_AREVT */
+ writew(151, CTRL_CORE_MPU_IRQ_154_REG); /* MCASP3_IRQ_AXEVT */
+ writew(156, CTRL_CORE_MPU_IRQ_156_REG); /* MCASP6_IRQ_AREVT */
+ writew(157, CTRL_CORE_MPU_IRQ_157_REG); /* MCASP6_IRQ_AXEVT */
+ writew(251, CTRL_CORE_MPU_IRQ_136_REG); /* MAILBOX5 */
+ writew(255, CTRL_CORE_MPU_IRQ_141_REG); /* MAILBOX6 */
+ writew(396, CTRL_CORE_MPU_IRQ_142_REG); /* IPU2 MMU */
+ writew(145, CTRL_CORE_MPU_IRQ_143_REG); /* DSP1 MMU1 */
+ writew(146, CTRL_CORE_MPU_IRQ_144_REG); /* DSP2 MMU0 */
+ writew(147, CTRL_CORE_MPU_IRQ_145_REG); /* DSP2 MMU1 */
+ writew(343, CTRL_CORE_MPU_IRQ_124_REG); /* QSPI */
+}
+
+static void set_crossbar_sdma_dreq()
+{
+ /* SDMA_DREQ mapping to CROSSBAR_IRQ */
+ writew(132, CTRL_CORE_DMA_SYSTEM_DREQ_79_REG); /* MCASP3_DREQ_RX */
+ writew(133, CTRL_CORE_DMA_SYSTEM_DREQ_78_REG); /* MCASP3_DREQ_TX */
+ writew(138, CTRL_CORE_DMA_SYSTEM_DREQ_63_REG); /* MCASP6_DREQ_RX */
+ writew(139, CTRL_CORE_DMA_SYSTEM_DREQ_62_REG); /* MCASP6_DREQ_TX */
+}
+
+void set_crossbar_regs(void)
+{
+ set_crossbar_mpu_irq();
+ set_crossbar_sdma_dreq();
+}