HACK: ARM: DRA7xx: Add Ethernet crossbar setting

[glsdk/glsdk-u-boot.git] / nand_spl / nand_boot_fsl_elbc.c

diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 0d2378ee894d29d084fe19ab7bcd1c684ff28834..e9d649743eeef51f6c5175249493a042b48ca26b 100644 (file)
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -25,7 +25,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/immap_83xx.h>
 #include <asm/fsl_lbc.h>
 #include <linux/mtd/nand.h>
 
@@ -33,7 +32,7 @@
 
 static void nand_wait(void)
 {
-       lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
+       fsl_lbc_t *regs = LBC_BASE_ADDR;
 
        for (;;) {
                uint32_t status = in_be32(&regs->ltesr);
@@ -50,13 +49,13 @@ static void nand_wait(void)
 
 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 {
-       lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
-       uchar *buf = (uchar *)CFG_NAND_BASE;
-       int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
-       int block_shift = large ? 17 : 14;
-       int block_size = 1 << block_shift;
-       int page_size = large ? 2048 : 512;
-       int bad_marker = large ? page_size + 0 : page_size + 5;
+       fsl_lbc_t *regs = LBC_BASE_ADDR;
+       uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
+       const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
+       const int block_shift = large ? 17 : 14;
+       const int block_size = 1 << block_shift;
+       const int page_size = large ? 2048 : 512;
+       const int bad_marker = large ? page_size + 0 : page_size + 5;
        int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
        int pos = 0;
 
@@ -67,39 +66,42 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 
        if (large) {
                fmr |= FMR_ECCM;
-               out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
-                                    (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
-               out_be32(&regs->fir,
-                        (FIR_OP_CW0 << FIR_OP0_SHIFT) |
-                        (FIR_OP_CA  << FIR_OP1_SHIFT) |
-                        (FIR_OP_PA  << FIR_OP2_SHIFT) |
-                        (FIR_OP_CW1 << FIR_OP3_SHIFT) |
-                        (FIR_OP_RBW << FIR_OP4_SHIFT));
+               __raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
+                       (NAND_CMD_READSTART << FCR_CMD1_SHIFT),
+                       &regs->fcr);
+               __raw_writel(
+                       (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+                       (FIR_OP_CA  << FIR_OP1_SHIFT) |
+                       (FIR_OP_PA  << FIR_OP2_SHIFT) |
+                       (FIR_OP_CW1 << FIR_OP3_SHIFT) |
+                       (FIR_OP_RBW << FIR_OP4_SHIFT),
+                       &regs->fir);
        } else {
-               out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
-               out_be32(&regs->fir,
-                        (FIR_OP_CW0 << FIR_OP0_SHIFT) |
-                        (FIR_OP_CA  << FIR_OP1_SHIFT) |
-                        (FIR_OP_PA  << FIR_OP2_SHIFT) |
-                        (FIR_OP_RBW << FIR_OP3_SHIFT));
+               __raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, &regs->fcr);
+               __raw_writel(
+                       (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+                       (FIR_OP_CA  << FIR_OP1_SHIFT) |
+                       (FIR_OP_PA  << FIR_OP2_SHIFT) |
+                       (FIR_OP_RBW << FIR_OP3_SHIFT),
+                       &regs->fir);
        }
 
-       out_be32(&regs->fbcr, 0);
-       clrsetbits_be32(&regs->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
+       __raw_writel(0, &regs->fbcr);
 
        while (pos < uboot_size) {
                int i = 0;
-               out_be32(&regs->fbar, offs >> block_shift);
+               __raw_writel(offs >> block_shift, &regs->fbar);
 
                do {
                        int j;
                        unsigned int page_offs = (offs & (block_size - 1)) << 1;
 
-                       out_be32(&regs->ltesr, ~0);
-                       out_be32(&regs->lteatr, 0);
-                       out_be32(&regs->fpar, page_offs);
-                       out_be32(&regs->fmr, fmr);
-                       out_be32(&regs->lsor, 0);
+                       __raw_writel(~0, &regs->ltesr);
+                       __raw_writel(0, &regs->lteatr);
+                       __raw_writel(page_offs, &regs->fpar);
+                       __raw_writel(fmr, &regs->fmr);
+                       sync();
+                       __raw_writel(0, &regs->lsor);
                        nand_wait();
 
                        page_offs %= WINDOW_SIZE;
@@ -120,7 +122,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 
                        pos += page_size;
                        offs += page_size;
-               } while (offs & (block_size - 1));
+               } while ((offs & (block_size - 1)) && (pos < uboot_size));
        }
 }
 
@@ -133,18 +135,21 @@ void nand_boot(void)
 {
        __attribute__((noreturn)) void (*uboot)(void);
 
-       udelay(1000000);
-
        /*
         * Load U-Boot image from NAND into RAM
         */
-       nand_load(CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
-                 (uchar *)CFG_NAND_U_BOOT_DST);
+       nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+                 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 
        /*
         * Jump to U-Boot image
         */
        puts("transfering control\n");
-       uboot = (void *)CFG_NAND_U_BOOT_START;
+       /*
+        * Clean d-cache and invalidate i-cache, to
+        * make sure that no stale data is executed.
+        */
+       flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+       uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
        uboot();
 }