]> Gitweb @ Texas Instruments - Open Source Git Repositories - git.TI.com/gitweb - glsdk/glsdk-u-boot.git/commitdiff
Merge remote-tracking branch 'u-boot/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 30 Sep 2012 21:49:17 +0000 (23:49 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 30 Sep 2012 21:49:17 +0000 (23:49 +0200)
15 files changed:
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-mx5/imx-regs.h
board/atmel/at91sam9x5ek/at91sam9x5ek.c
board/freescale/mx28evk/mx28evk.c
board/freescale/mx51evk/mx51evk.c
board/karo/tx25/lowlevel_init.S
drivers/mtd/nand/atmel_nand.c
drivers/mtd/spi/atmel.c
drivers/video/mxc_ipuv3_fb.c
include/configs/at91sam9261ek.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9x5ek.h
include/configs/mx28evk.h
include/configs/mx51evk.h
include/ipu_pixfmt.h

index fa1d4680416ff2d3470257cd007351650df441e6..a10d12d97dcdc9739de53e66db9e15cfadbb54f2 100644 (file)
@@ -30,6 +30,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <ipu_pixfmt.h>
 
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -138,3 +139,11 @@ u32 get_ahb_clk(void)
 
        return get_periph_clk() / (ahb_podf + 1);
 }
+
+#if defined(CONFIG_VIDEO_IPUV3)
+void arch_preboot_os(void)
+{
+       /* disable video before launching O/S */
+       ipuv3_fb_shutdown();
+}
+#endif
index d1ef15d043da143cd81b7b6d85ed86b8a75ef54d..46017f4ad062a5289e007ab4507bef43db6a5216 100644 (file)
 #define BOARD_REV_1_0           0x0
 #define BOARD_REV_2_0           0x1
 
+#define BOARD_VER_OFFSET       0x8
+
 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
index ae408bc9db1024407c9e9510029026d7414316a0..06028aa01e82fbf699441caf815dc125f65c80c4 100644 (file)
@@ -62,6 +62,10 @@ static void at91sam9x5ek_nand_hw_init(void)
        csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
        /* NAND flash on D16 */
        csa |= AT91_MATRIX_NFD0_ON_D16;
+
+       /* Configure IO drive */
+       csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
        writel(csa, &matrix->ebicsa);
 
        /* Configure SMC CS3 for NAND/SmartMedia */
index d782aea61b85537c83673b8b88d2937a5a4b5811..6e719ffc39f84136c1e69b8a532781ae0d5fbbeb 100644 (file)
@@ -100,19 +100,6 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_CMD_NET
 
-#define        MII_OPMODE_STRAP_OVERRIDE       0x16
-#define        MII_PHY_CTRL1                   0x1e
-#define        MII_PHY_CTRL2                   0x1f
-
-int fecmxc_mii_postcall(int phy)
-{
-       miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
-       miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
-       if (phy == 3)
-               miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
-       return 0;
-}
-
 int board_eth_init(bd_t *bis)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
@@ -152,24 +139,12 @@ int board_eth_init(bd_t *bis)
                return -EINVAL;
        }
 
-       ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-       if (ret) {
-               puts("FEC MXS: Unable to register FEC0 mii postcall\n");
-               return ret;
-       }
-
        dev = eth_get_dev_by_name("FEC1");
        if (!dev) {
                puts("FEC MXS: Unable to get FEC1 device entry\n");
                return -EINVAL;
        }
 
-       ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-       if (ret) {
-               puts("FEC MXS: Unable to register FEC1 mii postcall\n");
-               return ret;
-       }
-
        return ret;
 }
 
index 7a0682a7e96286f1f4b8e0547fd6972d19f802f2..a94701cbf1757d04ad0b894c039072d5cf8fd399 100644 (file)
@@ -60,6 +60,14 @@ int dram_init(void)
        return 0;
 }
 
+u32 get_board_rev(void)
+{
+       u32 rev = get_cpu_rev();
+       if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
+               rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
+       return rev;
+}
+
 static void setup_iomux_uart(void)
 {
        unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
index 823df10701e9c093c67ec04ea0cb134d8fbd1772..eb3f187806eac216b12030f6f53671735bb35ba5 100644 (file)
        write32 0x53f80064, 0x45600000
        write32 0x53f80008, 0x20034000
 
+       /*
+        * PCDR2: NFC = 33.25 MHz
+        * This is required for the NAND Flash of this board, which is a Samsung
+        * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
+        * the NFC driver in symmetric (i.e. one-cycle) mode.
+        */
+       write32 0x53f80020, 0x01010103
+
        /*
         * enable all implemented clocks in all three
         * clock control registers
index c6aa5db33c43666cd970cd1b214fbdf04b42a4a4..994dd9f0952516cf760b192841b9c9f0c04ec1ea 100644 (file)
@@ -652,8 +652,9 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
        sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
        host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
 
-       printk(KERN_INFO "Initialize PMECC params, cap: %d, sector: %d\n",
-                cap, sector_size);
+       MTDDEBUG(MTD_DEBUG_LEVEL1,
+               "Initialize PMECC params, cap: %d, sector: %d\n",
+               cap, sector_size);
 
        host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
        host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
index 1ecece0d7808269f55f1f702f39fb1e45d070566..006f6d5d04fcb2258b3014fa41a32bdbadd8fb56 100644 (file)
@@ -109,6 +109,14 @@ static const struct atmel_spi_flash_params atmel_spi_flash_table[] = {
                .nr_sectors             = 32,
                .name                   = "AT45DB642D",
        },
+       {
+               .idcode1                = 0x47,
+               .l2_page_size           = 8,
+               .pages_per_block        = 16,
+               .blocks_per_sector      = 16,
+               .nr_sectors             = 64,
+               .name                   = "AT25DF321",
+       },
 };
 
 static int at45_wait_ready(struct spi_flash *flash, unsigned long timeout)
@@ -510,11 +518,19 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode)
                        asf->flash.erase = dataflash_erase_p2;
                }
 
+               asf->flash.page_size = page_size;
+               asf->flash.sector_size = page_size;
                break;
 
        case DF_FAMILY_AT26F:
        case DF_FAMILY_AT26DF:
                asf->flash.read = spi_flash_cmd_read_fast;
+               asf->flash.write = spi_flash_cmd_write_multi;
+               asf->flash.erase = spi_flash_cmd_erase;
+               asf->flash.page_size = page_size;
+               asf->flash.sector_size = 4096;
+               /* clear SPRL# bit for locked flash */
+               spi_flash_cmd_write_status(&asf->flash, 0);
                break;
 
        default:
@@ -522,7 +538,6 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode)
                goto err;
        }
 
-       asf->flash.sector_size = page_size;
        asf->flash.size = page_size * params->pages_per_block
                                * params->blocks_per_sector
                                * params->nr_sectors;
index c38e22de1f340b914575b7c2e6191596d33fc419..47b336e7aa4fb7de28996b4921779162a42f3f27 100644 (file)
@@ -38,6 +38,7 @@
 #include "videomodes.h"
 #include "ipu.h"
 #include "mxcfb.h"
+#include "ipu_regs.h"
 
 static int mxcfb_map_video_memory(struct fb_info *fbi);
 static int mxcfb_unmap_video_memory(struct fb_info *fbi);
@@ -576,6 +577,25 @@ err0:
        return ret;
 }
 
+void ipuv3_fb_shutdown(void)
+{
+       int i;
+       struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
+
+       for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
+               struct fb_info *fbi = mxcfb_info[i];
+               if (fbi) {
+                       struct mxcfb_info *mxc_fbi = fbi->par;
+                       ipu_disable_channel(mxc_fbi->ipu_ch);
+                       ipu_uninit_channel(mxc_fbi->ipu_ch);
+               }
+       }
+       for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
+               __raw_writel(__raw_readl(&stat->int_stat[i]),
+                            &stat->int_stat[i]);
+       }
+}
+
 void *video_hw_init(void)
 {
        int ret;
index 1e1fbe56d711fdc904516d952c645436671076be..611e3e253297ccb6f68adaa95a4be741f4f65fec 100644 (file)
@@ -48,6 +48,8 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 
+#define CONFIG_OF_LIBFDT
+
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_SYS_TEXT_BASE           0x21f00000
 
index 4ca280a7fff678b5fe7f08c027949e93b2ddbc94..e988d8141078afaae38faf57f192894ea6eb073d 100644 (file)
@@ -47,6 +47,8 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
+#define CONFIG_OF_LIBFDT
+
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
 #define CONFIG_AT91_GPIO
index 1ceb31a0f4e1b4695f0f391bbfc95dc4e89a3d08..cbdc3e93cbfd841287a93569499860f56fabbd26 100644 (file)
@@ -42,6 +42,8 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
+#define CONFIG_OF_LIBFDT
+
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
 #define CONFIG_AT91_GPIO
index dffb744c3dc0fe2e007e9cc7f0756b1976f7f12c..7cdbec68deac5191afa2246a5340d50947748591 100644 (file)
@@ -63,6 +63,7 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_USB
index ba4a4a623c10403fdd9aa196fb4a0b2044bcc2be..7b027b42acd8d403633c5cb1dca9b6bb04ee2b15 100644 (file)
@@ -44,6 +44,7 @@
 #define CONFIG_CMDLINE_TAG                     /* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
 
 #define CONFIG_OF_LIBFDT
 
index 0019898d51087f223c815a8c676bcbab9aa9ac55..4baa71187d9c1febd18980cbbc50d069ebb0b224 100644 (file)
@@ -77,5 +77,6 @@
 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
 
 int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
+void ipuv3_fb_shutdown(void);
 
 #endif